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products and specifications discussed herein ar e subject to change by micron without notice. 512mb: x4, x8, x16 ddr sdram features 09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_1.fm - rev. j 1/06 en 1 ?2000?2005 micron technology, inc. all rights reserved. double data rate (ddr) sdram mt46v128m4 ? 32 meg x 4 x 4 banks mt46v64m8 ? 16 meg x 8 x 4 banks mt46v32m16 ? 8 meg x 16 x 4 banks for the latest data sheet, refer to micron?s web site: www.micron.com/ddrsdram features ?v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v ?v dd = +2.6v 0.1v, v dd q = +2.6v 0.1v (ddr400) ? bidirectional data strobe (dqs) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two ? one per byte) ? internal, pipelined do uble-data-rate (ddr) architecture; two data accesses per clock cycle ? differential clock inputs (ck and ck#) ? commands entered on each positive ck edge ? dqs edge-aligned with data for reads; center- aligned with data for writes ? dll to align dq and dqs transitions with ck ? four internal banks for concurrent operation ? data mask (dm) for masking write data (x16 has two ? one per byte) ? programmable burst lengths: 2, 4, or 8 ? auto refresh and self refresh modes ? longer lead tsop for improved reliability (ocpl) ? 2.5v i/o (sstl_2 compatible) ? concurrent auto precharge option is supported ? t ras lockout supported ( t rap = t rcd) options marking ? configuration 128 meg x 4 (32 meg x 4 x 4 banks) 128m4 64 meg x 8 (16 meg x 8 x 4 banks) 64m8 32 meg x 16 (8 meg x 16 x 4 banks) 32m16 ?plastic package 66-pin tsop tg 66-pin tsop lead-free p 60-ball fbga (10 x 12.5mm) fn 60-ball fbga (10 x 12.5mm) lead-free bn ? timing ? cycle time 5ns @ cl = 3 (ddr400b) -5b 6ns @ cl = 2.5 (ddr333) (fbga only) -6 6ns @ cl = 2.5 (ddr333) (tsop only) -6t 7.5ns @ cl = 2 (ddr266) -75e 7.5ns @ cl = 2 (ddr266a) -75z 7.5ns @ cl = 2.5 (ddr266b) -75 ? self refresh standard none low-power self refresh l ? temperature rating standard (0c to +70c) none industrial (-40 c to +85 c) it ? revision x4, x8, x16 :c x4, x8 :d x4, x8, x16 :f table 1: addressing configuration 128 meg x 4 64 meg x 8 32 meg x 16 configuration 32 meg x 4 x 4 banks 16 meg x 8 x 4 banks 8 meg x 16 x 4 banks refresh count 8k 8k 8k row addressing 8k (a0?a12) 8k (a0?a12) 8k (a0?a12) bank addressing 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) column addressing 4k (a0-a9, a11, a12) 2k (a0?a9, a11) 1k (a0?a9) table 2: key timing parameters cl = cas (read) latency; data-out window is min clock rate with 50% duty cycle @ cl = 2, cl = 2.5, or cl = 3 speed grade clock rate data-out window access window dqs?dq skew cl = 2 cl = 2.5 cl = 3 -5b 133 mhz 167 mhz 200 mhz 1.6ns 0.70ns +0.40ns -6 133 mhz 167 mhz na 2.1ns 0.70ns +0.40ns 6t 133 mhz 167 mhz na 2.0ns 0.70ns +0.45ns -75e/-75z 133 mhz 133 mhz na 2.5ns 0.75ns +0.50ns -75 100 mhz 133 mhz na 2.5ns 0.75ns +0.50ns
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_1.fm - rev. j 1/06 en 2 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram fbga part number system figure 1: 512mb ddr sdram part numbers fbga part number system due to space limitations, fbga-packaged components have an abbreviated part mark- ing that is different from the part number. for a quick conversion of an fbga code, see the fbga part marking decoder at: www.micron.com/decoder . table 1: speed grade backward compatibility marking pc3200 (3-3-3) pc2700 (2.5-3-3) pc2100 (2-2-2) pc2100 (2-3-3) pc2100 (2.5-3-3) pc1600 (2-2-2) -5b yes yes yes yes yes yes -6 yes yes yes yes yes -6t yes yes yes yes yes -75e yes yes yes yes -75z yes yes yes -75 yes yes -5b -6/-6t -75e -75z -75 -75 l special options standard low power speed grade t ck = 5ns, cl = 3 t ck = 6ns, cl = 2.5 t ck = 6ns, cl = 2.5 t ck = 7.5ns, cl = 2 t ck = 7.5ns, cl = 2 t ck = 7.5ns, cl = 2.5 -5b -6 -6t -75e -75z -75 it operating temp standard industrial temp revision x4, x8, x16 x4, x8 x4, x8, x16 :c :d :f example part number: mt46v32m16tg-75z - configuration mt46v pa ckage speed : revision sp. op. temp. configuration 128 meg x4 64 meg x8 32 meg x16 128m4 64m8 32m16 package 400 mil tsop 400 mil tsop lead-free 10 x 12.5mm fbga 10 x 12.5mm fbga lead-free tg p fn bn
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16toc.fm - rev. j 1/06 en 3 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram table of contents table of contents fbga part number system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 general notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 ball/pin assignments and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 cas (read) latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 output drive strength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 dll enable/disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 bank/row activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 power-down (cke not active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16lof.fm - rev. j 1/06 en 4 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram list of figures list of figures figure 1: 512mb ddr sdram part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 figure 2: 128 meg x 4 functional block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3: 64 meg x 8 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: 32 meg x 16 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: 66-pin tsop pin assignment (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 6: 60-ball fbga ball assignment (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 8: cas latency (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 9: extended mode register definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 10: activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 11: example: meeting t rcd ( t rrd) min when 2 < t rcd ( t rrd) min/ t ck 3 . . . . . . . . . . . . . . . . . . . . . .26 figure 12: read command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 13: read burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 14: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 15: nonconsecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 16: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 17: terminating a read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 18: read-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 19: read-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 20: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 21: write burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 23: nonconsecutive write-to-write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 24: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 26: write-to-read ? interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 27: write-to-read ? odd number of data, interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 28: write-to-precharge ? uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 29: write-to-precharge ? interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 30: write-to-precharge ? odd number of data, interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 31: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 32: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 33: input voltage waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 34: sstl_2 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 35: derating data valid window ( t qh - t dqsq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 figure 36: full drive pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 37: full drive pull-up characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 38: reduced drive pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 39: reduced drive pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 40: x4, x8 data output timing ? t dqsq, t qh, and data valid window . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 figure 41: x16 data output timing ? t dqsq, t qh, and data valid window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 figure 42: data output timing ? t ac and t dqsck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 figure 43: data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 figure 44: initialization flow di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 figure 45: initialize and load mode regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 figure 46: power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 47: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 figure 48: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 figure 49: bank read - without auto precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 figure 50: bank read - with auto precharg e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 figure 51: bank write - without auto precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 figure 52: bank write - with auto precharg e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 figure 53: write - dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16lof.fm - rev. j 1/06 en 5 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram list of figures figure 54: 66-pin plastic tsop (400 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 figure 55: 60-ball fbga (10 x 12.5mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16lot.fm - rev. j 1/06 en 6 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram list of tables list of tables table 1: addressing configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 1: speed grade backward compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 2: ball/pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 3: reserved nc balls and pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 4: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 5: cas latency (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 6: truth table ? commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 7: truth table ? dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 8: truth table ? cke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 9: truth table ? current state bank n - command to bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 10: truth table ? current state bank n - command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 13: dc electrical characteristics an d operating conditions (-6, -6t, -75e, -75z, -75) . . . . . . . . . . . . . . .54 table 14: dc electrical characteristics and operating conditions (-5b ddr400) . . . . . . . . . . . . . . . . . . . . . . . .55 table 15: ac input operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 16: clock input operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 17: capacitance (x4, x8 tsop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 18: capacitance (x4, x8 fbga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 19: capacitance (x16 tsop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 20: capacitance (x16 fbga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 21: i dd specifications and conditions (x4, x8; -5b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 22: i dd specifications and conditions (x4, x8; -6/-6t/-75e/-75z/-75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 23: i dd specifications and conditions (x16; -5b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 24: i dd specifications and conditions (x16; -6/-6t/-75e/-75z/-75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 25: i dd test cycle times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 26: electrical characterist ics & recommended ac operating conditions (- 5b) . . . . . . . . . . . . . . . . . . . .64 table 27: electrical characteristics an d recommended ac operating conditions (-6/-6t/-75e) . . . . . . . . . .66 table 28: electrical characteristics and recommended ac operating conditions (-75z/-75) . . . . . . . . . . . . .68 table 29: input slew rate derating values for addresses and comma nds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 30: input slew rate derating values for dq, dqs, and dm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 31: normal output drive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 table 32: reduced output drive characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 7 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram general description general description the 512mb ddr sdram is a high-speed cmos, dynamic random-access memory con- taining 536,870,912 bits. it is internally configured as a quad-bank dram. the 512mb ddr sdram uses a double data ra te architecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512mb ddr sdram effectiv ely consists of a single 2 n - bit wide, one-clock-cycle data transfer at the internal dram core and two correspond- ing n -bit wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writ es. the x16 offering has two data strobes, one for the lower byte and one for the upper byte. the 512mb ddr sdram operates from a differen tial clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. com- mands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdra m are burst oriented; accesses start at a selected location and continue for a prog rammed number of locations in a programmed sequence. accesses begin with the registrati on of an active command, which may then be followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4, or 8 locations. an auto precharge function may be enabled to provide a self-timed row pre- charge that is initiated at the end of the burst access. as with standard sdr sdrams, the pipeline d, multibank architec ture of ddr sdrams allows for concurrent operation, thereby pr oviding high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power-saving power-down mode. all inputs are compatible with the jedec standard for sstl_2. all full drive option outputs are sstl_2, class ii compatible. general notes ? the functionality and the timi ng specifications discussed in this data sheet are for the dll-enabled mode of operation. ? throughout the data sheet, the various figures and text refer to dqs as ?dq.? the dq term is to be interpreted as any and all dq collectively, unless specifically stated oth- erwise. additionally, the x16 is divided into two bytes, the lower byte and upper byte. for the lower byte (dq0?dq7) dm refers to ldm and dqs refers to ldqs. for the upper byte (dq8?dq15) dm refers to udm and dqs refers to udqs. ? complete functionality is described throug hout the document and any page or dia- gram may have been simplified to convey a topic and may not be inclusive of all requirements. ? any specific requirement takes precedence over a general statement.
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 8 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram general description figure 2: 128 meg x 4 functional block diagram figure 3: 64 meg x 8 functional block diagram 13 ras# cas# row- address mux ck cs# we# ck# control logic column- address counter/ latch mode registers 12 command decode a0-a12, ba0, ba1 cke 13 address register 15 2048 (x8) 16384 i/o gating dm mask logic column decoder bank0 memory array (8,192 x 2,048 x 8) bank0 row- address latch & decoder 8192 sense amplifiers bank control logic 15 bank1 bank2 bank3 13 11 1 2 2 refresh counter 4 4 4 1 input registers 1 1 1 1 rcvrs 1 8 8 2 8 clk out data dqs mask data ck ck col0 clk in drvrs dll mux dqs generator 4 4 4 4 4 8 dq0? dq3 dqs dm 1 read latch write fifo & drivers col0 13 ras# cas# row- address mux ck cs# we# ck# control logic column- address counter/ latch mode registers 11 command decode a0-a12, ba0, ba1 cke 13 address register 15 1024 (x16) 16384 i/o gating dm mask logic column decoder bank0 memory array (8,192 x 1,024 x 16) bank0 row- address latch & decoder 8192 sense amplifiers bank control logic 15 bank1 bank2 bank3 13 10 2 2 refresh counter 8 8 8 1 input registers 1 1 1 1 rcvrs 1 16 16 2 16 clk out data dqs mask data ck ck clk in drvrs dll mux dqs generator 8 8 8 8 8 16 dq0? dq7 dqs 1 read latch write fifo & drivers 1 col0 col0 dm
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 9 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram general description figure 4: 32 meg x 16 functional block diagram 13 ra s # c a s # row- addre ss mux c k cs # we# c k# c ontrol lo g i c c olumn- addre ss c ounter/ lat c h mode re g i s ter s 10 c ommand de c ode a0-a12, ba0, ba1 c ke 13 addre ss re g i s ter 15 512 (x32) 1 6 384 i/o g atin g dm ma s k lo g i c c olumn de c oder bank0 memory array (8,192 x 512 x 32) bank0 row- addre ss lat c h & de c oder 8192 s en s e amplifier s bank c ontrol lo g i c 15 bank1 bank2 bank3 13 9 2 2 refre s h c ounter 1 6 1 6 1 6 2 input re g i s ter s 2 2 2 2 r c vr s 2 32 32 4 32 c lk out data dq s ma s k data c k c ?k c lk in drvr s dll mux dq s g enerator 1 6 1 6 1 6 1 6 1 6 32 dq0 - dq15 ldq s udq s 2 read lat c h write fifo & driver s 1 c ol0 c ol0 ldm, udm
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 10 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram ball/pin assignments and descriptions ball/pin assignments and descriptions table 2: ball/pin descriptions fbga numbers tsop numbers symbol type description g2, g3 45, 46 ck, ck# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossi ng of the positive edge of ck and negative edge of ck#. output data (dq and dqs) is referenced to the crossings of ck and ck#. h3 44 cke input clock enable: cke high activates an d cke low deactivates the internal clock, input buffers and output drivers. taking cke low provides precharge power-down and self refr esh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down entry and exit, an d for self refresh entry. cke is asynchronous for self refresh exit and for di sabling the outputs. cke must be maintained hi gh throughout read an d write accesses. input buffers (excluding ck, ck# and cke) are disabled du ring power-down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_2 input but will detect an lvcmos low level after v dd is applied and until cke is first brought high, after which it becomes a sstl_2 input only. h8 24 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands ar e masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. h7, g8, g7 23, 22, 21 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. 3f 47 dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high al ong with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading is de signed to match that of dq and dqs pins. for the x16, ldm is dm fo r dq0?dq7 and udm is dm for dq8? dq15. pin 20 is a nc on x4 and x8. f7, 3f 20, 47 ldm, udm j8, j7 26, 27 ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. k7, l8, l7, m8, m2, l3, l2, k3, k2, j3, k8, j2,h2 29, 30, 31, 32, 35, 36, 37, 38, 39, 40, 28 41, 42 a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/ write commands, to select one location out of the memo ry array in the respective bank. a10 sampled during a pr echarge command determines whether the precharge applies to one bank (a10 lo w, bank selected by ba0, ba1) or all banks (a10 high). the address inpu ts also provide the op-code during a mode register set command. ba0 and ba1 define which mode register (mode register or extended mo de register) is loaded during the load mode register (lmr) command.
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 11 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram ball/pin assignments and descriptions a8, b9, b7, c9, c7, d9, d7, e9, e1, d3, d1, c3, c1, b3, b1, a2 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 dq0?dq2 dq3?dq5 dq6?dq8 dq9?dq11 dq12?dq14 dq15 i/o data input/output: data bus for x16 ? 14, 17, 25, 43, 53 nc ? no connect for x16 these pins should be left unconnected. a8, b7, c7, d7, d3, c3, b3, a2 2, 5, 8, 11, 56, 59, 62, 65 dq0?dq2 dq3?dq5 dq6, dq7 i/o data input/output: data bus for x8 b1, b9, c1, c9, d1, d9, e1, e7, e9, f7 4, 7, 10, 13, 14, 16, 17, 20, 25, 43, 53, 54, 57, 60, 63, nc ? no connect for x8 these pins should be left unconnected. b7, d7, d3, 5, 11, 56, dq0?dq2 i/o data input/output: data bus for x4 b3 62 dq3 b1, b9, c1, c9, d1, d9, e1, e7, e9, f7 4, 7, 10, 13, 14, 16, 17, 20, 25, 43, 53, 54, 57, 60, 63 nc ? no connect for x4 these pins should be left unconnected. a2, a8, c3, c7 2, 8, 59, 65 nf ? no function for x4 these pins should be left unconnected. e3 51 dqs i/o data strobe: output with read data, input with write data. dqs is edge- aligned with read data, centered in wr ite data. it is used to capture data. for the x16, ldqs is dqs for dq0? dq7 and udqs is dqs for dq8?dq15. pin 16 (e7) is nc on x4 and x8. e7 16 ldqs e3 51 udqs f9 19, 50 dnu ? do not use: must float to minimize noise on v ref . b2, d2, c8, e8, a9 3, 9, 15, 55, 61 v dd q supply dq power supply: +2.5v 0.2v (+2.6v 0.1v for ddr400). isolated on the die for improved noise immunity. a1, c2, e2, b8, d8 6, 12, 52, 58, 64 v ss q supply dq ground. isolated on the die for improved noise immunity. f8, m7, a7 1, 18, 33 v dd supply power supply: +2.5v 0.2v. (+2.6v 0.1v for ddr400) a3, f2, m3 34, 48, 66 v ss supply ground. f1 49 v ref supply sstl_2 reference voltage. table 3: reserved nc balls and pins this table defines specific nc pins; nc pins not listed may also be reserved for other uses now or in the future fbga numbers tsop numbers symbol type description f9 17 a13 i address input a13 for 1gb devices. table 2: ball/pin de scriptions (continued) fbga numbers tsop numbers symbol type description
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 12 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram ball/pin assignments and descriptions figure 5: 66-pin tsop pin assignment (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 nc v ss q udqs dnu v ref v ss udm ck# ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss x16 v dd dq0 v dd q dq1 dq2 vssq dq3 dq4 v dd q dq5 dq6 vssq dq7 nc v dd q ldqs nc v dd dnu ldm we# cas# ras# cs# nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd x16 v ss dq7 v ss q nc dq6 v dd q nc dq5 v ss q nc dq4 v dd q nc nc v ss q dqs dnu v ref v ss dm ck# ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss x8 x4 v ss nf v ss q nc dq3 v dd q nc nf v ss q nc dq2 v dd q nc nc v ss q dqs dnu v ref v ss dm ck# ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 v ss v dd dq0 v dd q nc dq1 v ss q nc dq2 v dd q nc dq3 v ss q nc nc v dd q nc nc v dd dnu nc we# cas# ras# cs# nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd x8 x4 v dd nf v dd q nc dq0 v ss q nc nf v dd q nc dq1 v ss q nc nc v dd q nc nc v dd dnu nc we# cas# ras# cs# nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 13 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram ball/pin assignments and descriptions figure 6: 60-ball fbga ball assignment (top view) v ss q dq14 dq12 dq10 dq8 v ref dq15 v dd q v ss q v dd q v ss q v ss ck a12 a11 a8 a6 a4 v ss dq13 dq11 dq9 udqs udm ck# cke a9 a7 a5 v ss v dd dq2 dq4 dq6 ldqs ldm we# ras# ba1 a0 a2 v dd dq0 v ss q v dd q v ss q v dd q v dd cas# cs# ba0 a10 a1 a3 v dd q dq1 dq3 dq5 dq7 nc x16 (top view) v ss q nc nc nc nc v ref nf v dd q v ss q v dd q v ss q v ss ck a12 a11 a8 a6 a4 v ss dq3 nf dq2 dqs dm ck# cke a9 a7 a5 v ss v dd dq0 nf dq1 nc nc we# ras# ba1 a0 a2 v dd nf v ss q v dd q v ss q v dd q v dd cas# cs# ba0 a10 a1 a3 v dd q nc nc nc nc nc x4 (top view) v ss q nc nc nc nc v ref dq7 v dd q v ss q v dd q v ss q v ss ck a12 a11 a8 a6 a4 v ss dq6 dq5 dq4 dqs dm ck# cke a9 a7 a5 v ss v dd dq1 dq2 dq3 nc nc we# ras# ba1 a0 a2 v dd dq0 v ss q v dd q v ss q v dd q v dd cas# cs# ba0 a10 a1 a3 v dd q nc nc nc nc nc x8 (top view) a 12 3456789 b c d e f g h j k l m a 12 3456789 b c d e f g h j k l m a 12 3456789 b c d e f g h j k l m
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 14 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram functional description functional description the 512mb ddr sdram is a high-speed cmos, dynamic random-access memory con- taining 536,870,912 bits. the 512mb ddr sdram is internally configured as a quad- bank dram. the 512mb ddr sdram uses a double data ra te architecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n -prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512mb ddr sdram consists of a single 2 n -bit wide, one-clock-cycle data transfer at the in ternal dram core and two corresponding n -bit wide, one-half-clock-cycle data transfers at the i/o pins. read and write accesses to the ddr sdra m are burst oriented; accesses start at a selected location and continue for a prog rammed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0?a12 select the row). the address bits registered coincident with the read or write command are used to select the star ting column location for the burst access. prior to normal operation, the ddr sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, com- mand descriptions, and device operation. initialization ddr sdrams must be powered up and initia lized in a predefined manner. operational procedures other than those specified may result in undefined operation. power must first be applied to v dd and v dd q simultaneously, and then to v ref (and to the system v tt ). v tt must be applied after v dd q to avoid device latch-up, which may cause perma- nent damage to the device. v ref can be applied any time after v dd q but is expected to be nominally coin cident with v tt . except for cke, inputs are not recognized as valid until after v ref is applied. cke is an sstl_2 input but will detect an lvcmos low level after v dd is applied. after cke passes through v ih , it will transition to a sstl 2 signal and remain as such until power is cycled. maintaining an lvcmos low level on cke during power-up is required to ensure that the dq and dqs outputs will be in the high- z state, where they will remain until driven in normal operation (by a read access). after all power supply and reference voltages ar e stable, and the clock is stable, the ddr sdram requires a 200s delay prior to applying an executable command. once the 200s delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a pre- charge all command should be applied. next a load mode register command should be issued for the extended mode register (ba1 low and ba0 high) to enable the dll, followed by another load mode regi ster command to the mode register (ba0/ ba1 both low) to reset the dll and to program the operating parameters. two-hun- dred clock cycles are required between the dll reset and any read command. a pre- charge all command should then be applied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed ( t rfc must be sat- isfied.) addition ally, a load mode register comman d for the mode register with the reset dll bit deactivated (i.e., to program operating parameters without resetting the dll) is required. following these requirements, the ddr sdram is ready for normal operation.
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 15 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram register definition register definition mode register the mode register is used to define the sp ecific mode of operation of the ddr sdram. this definition includes the selection of a burst length, a burst type, a cas latency and an operating mode, as shown in figure 7 on page 16. the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit a8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. the mode register mu st be loaded (reloaded) when all banks are idle and no bursts are in progress, and the co ntroller must wait the specified time before initiating the subsequent operat ion. violating either of these requirements will result in unspecified operation. mode register bits a0?a2 specify the burst le ngth, a3 specifies the type of burst (sequen- tial or interleaved), a4?a6 specify the cas latency, and a7?a12 specify the operating mode. burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being programmable, as shown in figure 7 on page 16. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. bl = 2, bl = 4, or bl = 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses fo r that burst take place within this block, meaning that the burst will wrap within the bl ock if a boundary is reached. the block is uniquely selected by a1-a i when bl = 2, by a2?a i when bl = 4 and by a3?a i when bl = 8 (where a i is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 4 on page 17.
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 16 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram register definition figure 7: mode register definition burst type sequential interleaved cas latency reserved reserved 2 3 (ddr400 only) reserved reserved 2.5 reserved burst length cas latency bt 0 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 0 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 operating mode a10 a12 a11 ba0 ba1 10 11 12 13 0 14 operating mode normal operation normal operation/reset dll all other states reserved 0 1 - 0 0 - 0 0 - 0 0 - 0 0 - 0 0 - valid valid - m6-m0 m8 m7 m9 m10 m12 m11 burst length reserved 2 4 8 reserved reserved reserved reserved m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 0 1 0 1 mode register definition base mode register extended mode register reserved reserved m14 0 0 1 1 m13
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 17 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram register definition notes: 1. whenever a boundary of the block is reached within a given sequence above, the fol- lowing access wraps within the block. 2. for bl = 2, a1?a i select the two-data-element block; a0 selects the first access within the block. 3. for bl = 4, a2?a i select the four-data-element block; a0?a1 select the first access within the block. 4. for bl = 8, a3?a i select the eight-data-element block; a0?a2 select the first access within the block. table 4: burst definition burst length starting column address order of accesses within a burst type= sequential type= interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 18 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram register definition cas (read) latency the read latency is the delay, in clock cycles, between the registration of a read com- mand and the availability of the first bit of ou tput data. the latency can be set to 2, 2.5, or 3 (ddr400 only) clocks, as shown in figure 8. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . table 5 on page 19 indi- cates the operating frequencies at which ea ch cas latency (cl) setting can be used. reserved states should not be used, as unknown operation or incompatibility with future versions may result. figure 8: cas latency (cl) note: burst length = 4 in the cases shown; shown with nominal t ac, t dqsck, and t dqsq. c k c k# c ommand dq dq s c l = 2 read nop nop nop read nop nop nop c k c k# c ommand dq dq s c l = 2.5 t0 t1 t2 t2n t3 t3n t0 t1 t2 t2n t3 t3n don?t c are tran s itionin g data read nop nop nop c k c k# c ommand dq dq s c l = 3 t0 t1 t2 t3 t3n
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 19 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram extended mode register operating mode the normal operating mode is selected by issuing a mode register set command with bits a7?a12 each set to zero, and bits a0 ?a6 set to the desired values. a dll reset is initiated by issuing a mode register set co mmand with bits a7 and a9?a12 each set to zero, bit a8 set to one, and bits a0?a6 se t to the desired values. although not required by the micron device, jedec specifications recommend that a load mode register command resetting the dll should always be followed by a load mode register command selecting normal operating mode. all other combinations of values for a7?a12 are reserved for future use and/or test modes. test modes and reserved states should not be used, as unknown operation or incompatibility with future versions may result. extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable, and output drive strength. these functions are controlled via the bits shown in figure 9 on page 20. the extended mode register is programmed via the load mode register command to the mode register (with ba0 = 1 and ba1 = 0) and will re tain the stored information until it is pro- grammed again or the device loses power. the enabling of the dll should always be fol- lowed by a load mode register command to the mode register (ba0/ba1 both low) to reset the dll. the extended mode register must be loaded wh en all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subse- quent operation. violating either requirem ent could result in unspecified operation. output drive strength the normal drive strength for all outputs are specified to be sstl2, class ii. the x16 sup- ports a programmable option for reduced drive. this option is intended for the support of the lighter load and/or point-to-point environments. the selection of the reduced drive strength will alter the dq pins and dq s pins from sstl2, clas s ii drive strength to a reduced drive strength, which is approximat ely 54 percent of the sstl2, class ii drive strength. dll enable/disable when the part is running without the dll enab led, device functionality may be altered. the dll must be enabled for normal operation. dll enable is required during power- up initialization and upon returning to norm al operation after having disabled the dll for the purpose of debug or evaluation. (when the device exits self refresh mode, the dll is enabled automatically.) any time the dll is enabled, 200 clock cycles with cke high must occur before a read command can be issued. table 5: cas latency (cl) speed allowable operating clock frequency (mhz) cl = 2 cl = 2.5 cl = 3 -5b 75 f 133 75 f 167 133 f 200 -6/-6t 75 f 133 75 f 167 ? -75e 75 f 133 75 f 133 ? -75z 75 f 133 75 f 133 ? -75 75 f 100 75 f 133 ?
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 20 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram extended mode register figure 9: extended mode register definition notes: 1. the reduced drive strength option is av ailable on the x16 version. the reduced drive strength option is not supported on the x4 and x8 versions; contact mi cron for future sup- port of this feature. 2. the qfc# option is not supported. operating mode reserved reserved 0 ? 0 ? valid ? dll enable disable dll 1 0 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 9 7 654 3 8 2 1 0 0 1 e0 0 1 drive strength normal reduced e1 1 e2 2 e0 e1, operating mode a10 a11 a12 ba1 ba0 10 11 12 13 14 e3 e4 0 ? 0 ? 0 ? 0 ? 0 ? e6 e5 e7 e8 e9 0 ? 0 ? e10 e11 0 ? e12 ds 0 ? 0 1 0 1 mode register definition base mode register extended mode register reserved reserved m14 0 0 1 1 m13
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 21 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands commands table 6 and table 7 provide a quick reference of available commands. this is followed by a text description of each command. two ad ditional truth tables?table 9 on page 50, and table 10 on page 52? appear following ?operations? on page 25 and provide cur- rent state/next state information. notes: 1. deselect and nop are functionally interchangeable. 2. ba0?ba1 provide bank address and a0?a12 provide row address. 3. ba0?ba1 provide bank address; a0?a i provide column address, (where i = 9 for x16, i = 9, 11 for x8, and i = 9, 11, 12 for x4) a10 high enables the auto precharge feature (non per- sistent), and a10 low disables the auto precharge feature. 4. applies only to read bursts wi th auto precharge disabled; th is command is undefined (and should not be used) for read bursts with auto precha rge enabled and for write bursts. 5. a10 low: ba0-ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0-ba1 are ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressi ng while in self refresh mode, all inputs and i/os are ?don?t care? except for cke. 8. ba0?ba1 select either the mode register or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 se lect extended mode register; other combina- tions of ba0-ba1 are reserved). a0?a12 provide the op-code to be written to the selected mode register. table 6: truth table ? commands cke is high for all commands shown except self refresh name (function) cs# ras# cas# we# address notes deselect (nop) hxxx x 1 no operation (nop) l hhh x 1 active (select bank and activate row) l l h h bank/row 2 read (select bank and column, and start read burst) lhlhbank/col3 write (select bank and colu mn, and start write burst) l h l l bank/col 3 burst terminate lhhl x 4 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh (enter self refresh mode) lllh x 6, 7 load mode register llllop-code8 table 7: truth table ? dm operation used to mask write data; provided co incident with the corresponding data name (function) dm dq write enable l valid write inhibit h x
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 22 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands deselect the deselect function (cs# high) prevents new commands from being executed by the ddr sdram. the ddr sdram is effectiv ely deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the selected ddr sdram to perform a nop (cs# is low with ras#, cas#, and we# are high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode registers are loaded via inputs a0?a12. see mode register descriptions in "register definition" on page 15. the load mode register command can only be issued when all banks are idle, and a subseq uent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a sub- sequent access. the value on the ba0, ba1 inputs selects the bank, and the address pro- vided on inputs a0?a12 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a i (where i = 9 for x16; 9, 11 for x8; or 9, 11, 12 for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precha rged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a i (where i = 9 for x16; 9, 11 for x8; or 9, 11, 12 for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto pre- charge is selected, the row being accessed wi ll be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dq is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is regis- tered low, the corresponding data will be written to memory; if the dm signal is regis- tered high, the corresponding data inputs wi ll be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issu ed, except in the case of concur- rent auto precharge. with concurrent auto precharge, a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. input a10 determines whether
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 23 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands one or all banks are to be precharged, and in the case where only one bank is to be pre- charged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands bein g issued to that bank. a precharge com- mand will be treated as a nop if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual-bank precharge func- tion described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write com- mand is automatically performed upon comple tion of the read or write burst. auto precharge is either enabled or disabled fo r each individual read or write command. this device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. auto precharge ensures that the precharge is in itiated at the earliest valid stage within a burst. this ?earliest valid stage? is determ ined as if an explicit precharge command was issued at the earliest possible time, without violating t ras (min), as described for each burst type in ?operations? on page 25. the user must not issue another command to the same bank until the precharge time ( t rp) is completed. burst terminate the burst terminate command is used to tr uncate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst termi- nate command will be truncated, as shown in ?operations? on page 25. the open page from which the read burst was terminated remains open. auto refresh auto refresh is used during normal oper ation of the ddr sdram and is analogous to cas#-before-ras# (cbr) refresh in fpm/edo drams. this command is nonper- sistent, so it must be issued each time a refresh is required. all banks must be idle before an auto refresh command is issued. the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during an auto refresh command. the 512mb ddr sdram requires auto refresh cycles at an average interval of 7.8125s (max). to allow for improved efficiency in scheduling and switching between tasks, some flexi- bility in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted to any given dd r sdram, meaning that the maximum abso- lute interval between any auto refres h command and the next auto refresh command is 9 x 7.8125s (70.3s). jedec specif ications only allows 8 x 7.8125s; micron specification exceeds the jedec requirement by one clock. this maximum absolute interval is to allow future support for dll updates internal to the ddr sdram to be restricted to auto refresh cycles, without allowing excessive drift in t ac between updates. although not a jedec requirement, to provide for future functionality features, cke must be active (high) during the auto refresh period. the auto refresh period begins when the auto refresh command is registered and ends t rfc later.
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 24 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram commands self refresh the self refresh command can be used to re tain data in the ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). the dll is automatically dis- abled upon entering self refresh and is automatically enabled upon exiting self refresh (a dll reset and 200 clock cycles must then occur before a read command can be issued). input signals except cke are ?don?t care? during self refresh. v ref voltage is also required for the full duration of self refresh. the procedure for exiting self refresh requires a sequence of commands. first, ck and ck# must be stable prior to cke going back high. once cke is high, the ddr sdram must have nop commands issued for t xsnr because time is required for the comple- tion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nops for t xsnr time, then a dll re set (via the extended mode register) and nops for 200 additional cl ock cycles before applying any other com- mand.
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 25 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations operations bank/row activation before any read or write commands can be issued to a bank within the ddr sdram, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated, as shown in figure 10 on page 25. after a row is opened with an active command, a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 133 mhz clock (7.5ns period) results in 2.7 clocks rounded to 3. this is reflected in figure 11 on page 26, which covers any case where 2 < t rcd (min)/ t ck 3. (figure 11 also shows the same case for t rcd; the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?clo sed? (precharged). the minimum time inter- val between successive active commands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active co mmands to different banks is defined by t rrd. figure 10: activating a specific row in a specific bank cs # we# c a s # ra s # c ke a0-a12 ra ra = row a dd ress ba = bank a dd ress hi g h ba0, ba1 ba c k c k# don ? t c are
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 26 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 11: example: meeting t rcd ( t rrd) min when 2 < t rcd ( t rrd) min/ t ck 3 reads read bursts are initiated with a read co mmand, as shown in figure 12 on page 27. the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. note: for the read commands used in the following illustrations, auto precharge is dis- abled. during read bursts, the valid data-out elem ent from the starting column address will be available following the cas latency after the read command. each subsequent data- out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of ck and ck#). figure 13 on page 28 shows general timing for each possi- ble cas latency setting. dqs is driven by the ddr sdram along with output data. the initial low state on dqs is known as the re ad preamble; the low state coincident with the last data-out element is known as the read postamble. upon completion of a burst, assuming no other commands have been initiated, the dqs will go high-z. a detailed explanation of t dqsq (valid data-out skew), t qh (data-out window hold), the valid data window are depicted in figure 40 on page 79 and figure 41 on page 80. a detailed explanation of t dqsck (dqs transition skew to ck) and t ac (data-out transition skew to ck) is depicted in figure 42 on page 81. data from any read burst may be concatenated with or truncated with data from a sub- sequent read command. in either case, a cont inuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pa irs (pairs are required by the 2n-prefetch architecture). this is shown in figure 14 on page 29. a read command can be initiated on any clock cycle following a previous read command. nonconsecutive read data is shown for illustration in figure 15 on page 30. full-speed random read accesses within a page (or pages) can be performed, as shown in figure 16 on page 31. t c ommand ba0, ba1 a c ta c t nop rrd t r c d c k c k# bank x bank y a0-a12 row row nop rd/wr nop bank y c ol nop t0 t1 t2 t3 t4 t5 t 6 t7 don ? t c are nop
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 27 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations data from any read burst may be truncated with a burst terminate command, as shown in figure 17 on page 32. the burst terminate latency is equal to the read (cas) latency, i.e., the burst terminate command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). data from any read burst must be complete d or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown in figure 18 on page 33. the t dqss (nom) case is shown; the t dqss (max) case has a longer bus idle time. ( t dqss [min] and t dqss [max] are defined in the section on writes.) a read burst may be followed by, or tr uncated with, a precharge command to the same bank provided that auto precharge was not activated. the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). this is shown in figure 19 on page 34. following the precharge com- mand, a subsequent command to the same bank cannot be issued until both t ras and t rp has been met. part of the row precharge time is hidden during the access of the last data elements. figure 12: read command note: ca = column address; ba = bank address; en ap = enable auto precharge; and dis ap = disable auto precharge cs # we# c a s # ra s # c ke c a x4: a0?a9, a11, a12 x8: a0?a9, a11 x1 6 : a0?a9 a10 ba0,1 hi g h en ap di s ap ba x8: a12 x1 6 : a11, a12 c k c k# don ? t c are
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 28 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 13: read burst notes: 1. do n = data-out from column n . 2. bl = 4. 3. three subsequent elements of data-out appear in the programmed order following do n . 4. shown with nominal t ac, t dqsck, and t dqsq. ck ck# command read nop nop nop nop nop address bank a, col n read nop nop nop nop nop bank a , col n cl = 2 ck ck# command address dq dqs cl = 2.5 dq dqs do n do n t0 t1 t2 t3 t2n t3n t4 t5 t0 t1 t2 t3 t2n t3n t4 t5 don?t care transitioning data read nop nop nop nop nop bank a , col n ck ck# command address dq dqs cl = 3 do n t0 t1 t2 t3 t4n t3n t4 t5
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 29 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 14: consecutive read bursts notes: 1. do n (or b ) = data-out from column n (or column b ). 2. bl = 4 or 8 (if 4, the bursts are concatenated ; if 8, the second burst interrupts the first). 3. three subsequent elements of data-out appear in the programmed order following do n. 4. three (or seven) subsequent elements of data-out appear in the programmed order fol- lowing do b. 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies only when read co mmands are issued to same device. ck ck# command read nop read nop nop nop address bank, col n bank, col b command read nop read nop nop nop address bank, col n bank, col b cl = 2 ck ck# command address dq dqs cl = 2.5 dq dqs do n do b do n do b t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n don?t care transitioning data command read nop read nop nop nop address bank, col n bank, col b ck ck# command address dq dqs cl = 3 do n do b t0 t1 t2 t3 t3n t4 t5 t4n t5n
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 30 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 15: nonconsecutive read bursts notes: 1. do n (or b ) = data-out from column n (or column b ). 2. bl = 4 or 8 (if 4, the bursts are concatenated ; if 8, the second bu rst interrupts the first). 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. three (or seven) subsequent elements of data-out appear in the programmed order fol- lowing do b . 5. shown with nominal t ac, t dqsck, and t dqsq. c k c k# c ommand read nop nop nop nop nop addre ss bank, c ol n read bank, c ol b c ommand addre ss c l = 2 c k c k# c ommand addre ss dq dq s c l = 2.5 dq dq s do n t0 t1 t2 t3 t2n t3n t4 t5 t5n t 6 read nop nop nop nop nop bank, c ol n read bank, c ol b t0 t1 t2 t3 t2n t3n t4 t5 t5n t 6 do b do n do b don ? t c are tran s itionin g data c ommand addre ss c k c k# c ommand addre ss dq dq s c l = 3 read nop nop nop nop nop bank, c ol n read bank, c ol b t0 t1 t2 t3 t3n t4 t5 t 6 do n do b t4n
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 31 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 16: random read accesses notes: 1. do n (or x or b or g ) = data-out from column n (or column x or column b or column g ). 2. bl = 2, 4, or 8 (if 4 or 8, the following burst inte rrupts the previous). 3. n ' or x ' or b ' or g ' indicates the next data-out following do n or do x or do b or do g , respectively . 4. reads are to an active row in any bank . 5. shown with nominal t ac, t dqsck, and t dqsq. c k c k# c ommand read read read nop nop addre ss bank, c ol n bank, c ol x bank, c ol b bank, c ol x bank, c ol b read bank, c ol g c ommand addre ss c l = 2 c k c k# c ommand addre ss dq dq s c l = 2.5 dq dq s do n do x' do g do n' do b do x do b' do n do x' do n' do b do x do b' t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n read read read nop nop bank, c ol n read bank, c ol g t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n don ? t c are tran s itionin g data bank, c ol x bank, c ol b c ommand addre ss c k c k# c ommand addre ss dq dq s c l = 3 do n do x' do n' do b do x do b' read read read nop nop bank, c ol n read bank, c ol g t0 t1 t2 t3 t3n t4 t5 t4n t5n
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 32 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 17: terminating a read burst notes: 1. do n = data-out from column n . 2. bl = 4. 3. subsequent element of data-out appears in the programmed order following do n . 4. shown with nominal t ac, t dqsck, and t dqsq. 5. bst = burst terminate comm and, page remains open. ck ck# command read bst 5 nop nop nop nop address bank a , col n read bst 5 nop nop nop nop bank a , col n cl = 2 ck ck# command address dq dqs cl = 2.5 dq dqs do n do n t0 t1 t2 t3 t2n t4 t5 t0 t1 t2 t3 t2n t4 t5 don?t care transitioning data read bst 5 nop nop nop nop bank a , col n ck ck# command address dq dqs cl = 3 do n t0 t1 t2 t3 t3n t4 t5
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 33 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 18: read-to-write notes: 1. do n = data-out from column n . 2. di b = data-in from column b . 3. bl = 4 in the cases shown (applies for bursts of 8 as well; if bl = 2, the bst command shown can be nop). 4. one subsequent element of data-out app ears in the programmed order following do n. 5. data-in elements are applied following di b in the programmed order . 6. shown with nominal t ac, t dqsck, and t dqsq. 7. bst = burst terminate comm and, page remains open. c k c k# c ommand read b s t 7 nop nop nop addre ss bank, c ol n write bank, c ol b t0 t1 t2 t3 t2n t4 t5 t4n t5n dq dq s dm t (nom) dq ss di b c k c k# c ommand read b s t 7 nop write nop addre ss bank a , c ol n nop t0 t1 t2 t3 t3n t4 t5 t5n dq dq s do n dm don ? t c are tran s itionin g data do n t (nom) dq ss c k c k# c ommand read b s t 7 nop nop addre ss bank, c ol n write bank, c ol b t0 t1 t2 t3 t2n t4 t5 t5n dq dq s dm t (nom) dq ss di b do n nop c l = 2.5 c l = 2 t3n c l = 3 di b
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 34 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 19: read-to-precharge notes: 1. do n = data-out from column n . 2. bl = 4, or an interrupted burst of 8. 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. shown with nominal t ac, t dqsck, and t dqsq. 5. read to precharge equals two clocks, which allows two data pairs of data-out. 6. a read command with auto pr echarge enabled, provided t ras(min) is met, would cause a precharge to be performed at x number of clock cycles after the read command, where x = bl/2. 7. pre = precharge command; act = active command. ck ck# command 6 read nop pre nop nop act address bank a , col n bank a , ( a or all ) bank a , row read nop pre nop nop act bank a , col n cl = 2 t rp t rp ck ck# command 6 address dq dqs cl = 2.5 dq dqs do n do n t0 t1 t2 t3 t2n t3n t4 t5 t0 t1 t2 t3 t2n t3n t4 t5 bank a , ( a or all ) bank a , row read nop pre nop nop act bank a , col n t rp ck ck# command 6 address dq dqs cl = 3 do n t0 t1 t2 t3 t4n t3n t4 t5 bank a , ( a or all ) bank a , row don?t care transitioning data
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 35 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations writes write bursts are initiated with a write command, as shown in figure 20 on page 36. the starting column and bank addresses ar e provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst and after the t wr time. note: for the write commands used in the following illustrations, auto precharge is dis- abled. during write bursts, the first valid data-in element will be registered on the first rising edge of dqs following the write command, an d subsequent data elements will be reg- istered on successive edges of dqs. the low state on dqs between the write com- mand and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and th e first corresponding rising edge of dqs ( t dqss) is specified with a relatively wide range (from 75 percent to 125 per- cent of one clock cycle). all of the wr ite diagrams show the nominal case, and where the two extreme cases (i.e., t dqss [min] an d t dqss [max]) might not be intui- tive, they have also been included. figu re 21 on page 37 shows the nominal case and the extremes of t dqss for bl = 4. upon completion of a burst, assuming no other commands have been initiated, the dq wi ll remain high-z and any additional input data will be ignored. data for any write burst may be concatenat ed with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintained. the new write command can be issued on any positive edge of clock following the pre- vious write command. the first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new write command should be issued x cycles after the first write command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). figure 22 on page 38 shows concatenated burs ts of 4. an example of nonconsecutive writes is shown in figure 23 on page 39. full-speed random write accesses within a page or pages can be performed as shown in figure 24 on page 40.
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 36 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 20: write command note: ca = column address; ba = bank address; en ap = enable auto precharge; and dis ap = disable auto precharge. data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr should be met, as shown in figure 25 on page 41. data for any write burst may be truncated by a subsequent read command, as shown in figure 26 on page 42. note that only the data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent da ta-in should be masked with dm, as shown in figure 27 on page 43. data for any write burst may be followed by a subsequent precharge command. to follow a write without truncating the write burst, t wr should be met, as shown in figure 28 on page 44. data for any write burst may be truncated by a subsequent precharge command, as shown in figure 29 on page 45 and figure 30 on page 46. only the data-in pairs regis- tered prior to the t wr period are written to the internal array; any subsequent data-in should be masked with dm, as shown in figures 29 and 30. after the precharge com- mand, a subsequent command to the same bank cannot be issued until t rp is met. cs # we# c a s # ra s # c ke c a a10 ba0,1 hi g h en ap di s ap ba c k c k# don ? t c are x8: a12 x1 6 : a11, a12 x4: a0?a9, a11, a12 x8: a0?a9, a11 x1 6 : a0?a9
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 37 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 21: write burst notes: 1. di b = data-in for column b . 2. three subsequent elements of data-in are applied in the progra mmed order following di b . 3. an uninterrupted bl = 4 is shown. 4. a10 is low with the write comm and (auto precharge is disabled). dqs t dqss (max) t dqss (nom) t dqss (min) t dqss dm dq ck ck# command write nop nop address bank a , col b nop t0 t1 t2 t3 t2n dqs t dqss dm dq dqs t dqss dm dq di b di b di b don?t care transitioning data
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 38 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 22: consecutive write-to-write notes: 1. di b , etc. = data-i n for column b , etc. 2. three subsequent elements of data-in are applied in the progra mmed order following di b . 3. three subsequent elements of data-in are applied in the progra mmed order following di n . 4. an uninterrupted burst of 4 is shown . 5. each write command may be to any bank. ck ck# command write nop write nop nop address bank, col b nop bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t3n t1n dq dqs dm di n di b don?t care transitioning data t dqss t dqss (nom)
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 39 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 23: nonconsecutive write-to-write notes: 1. di b , etc. = data-i n for column b , etc. 2. three subsequent elements of data-in are applied in the progra mmed order following di b . 3. three subsequent elements of data-in are applied in the progra mmed order following di n . 4. an uninterrupted burst of 4 is shown . 5. each write command may be to any bank. ck ck# command write nop nop nop nop address bank, col b write bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t1n t5n dq dqs dm di n di b t dqss (nom) t dqss don?t care transitioning data
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 40 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 24: random write cycles notes: 1. di b , etc. = data-i n for column b , etc. 2. symbol b ' , etc. = the next da ta-in following di b , etc., according to the programmed burst order. 3. programmed bl = 2, 4, or 8 in cases shown. 4. each write command may be to any bank. t dqss (nom) ck ck# command write write write write nop address bank, col b bank, col x bank, col n bank, col g write bank, col a t0 t1 t2 t3 t2n t4 t5 t4n t1n t3n t5n dq dqs dm di b di b ' di x di x ' di n di n ' di a di a ' di g di g ' don?t care transitioning data
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 41 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 25: write-to-read ? uninterrupting notes: 1. di b = data-in for column b, do n = data-out for column n . 2. three subsequent elements of data-in are applied in the progra mmed order following di b . 3. an uninterrupted burst of 4 is shown. 4. t wtr is referenced from the first positive ck edge after the last data-in pair. 5. the read and write commands are to same device. however, the read and write com- mands may be to different devices, in which case t wtr is not required and the read com- mand could be applied earlier. 6. a10 is low with the write comm and (auto precharge is disabled). t dqss (nom) ck ck# command write nop nop read nop nop address bank a , col b bank a , col n nop t0 t1 t2 t3 t2n t4 t5 t1n t6 t6n t wtr cl = 2 dq dqs dm di b do n t dqss t dqss (min) cl = 2 dq dqs dm di b do n t dqss t dqss (max) cl = 2 dq dqs dm di b do n t dqss don?t care transitioning data
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 42 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 26: write-to-read ? interrupting notes: 1. di b = data-in for column b, do n = data-out for column n . 2. an interrupted burst of 4 is show n; two data elements are written. 3. one subsequent element of data-in is ap plied in the programme d order following di b . 4. t wtr is referenced from the first positive ck edge after the last data-in pair. 5. a10 is low with the write comm and (auto precharge is disabled). 6. dqs is required at t2 and t2n (nominal case) to register dm. 7. if the burst of 8 was used, dm and dqs wo uld be required at t3 and t3n because the read command would not mask these two data elements. t dqss (nom) ck ck# command write nop nop nop nop nop address bank a , col b bank a , col n read t0 t1 t2 t3 t2n t4 t5 t5n t1n t6 t6n t wtr cl = 2 dq dqs dm di b do n t dqss (min) cl = 2 dq dqs dm di b t dqss (max) cl = 2 dq dqs dm di b do n do n don?t care transitioning data t dqss t dqss t dqss t3n
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 43 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 27: write-to-read ? odd number of data, interrupting notes: 1. di b = data-in for column b, do n = data-out for column n . 2. an interrupted burst of 4 is sh own; one data el ement is written. 3. t wtr is referenced from the first positive ck edge after the last desired data-in pair (not the last two data elements). 4. a10 is low with the write comm and (auto precharge is disabled). 5. dqs is required at t1n, t2, and t2n (nominal case) to register dm. 6. if the burst of 8 was used, dm and dqs wo uld be required at t3?t3n because the read command would not mask these data elements. t dqss (nom) ck ck# command write nop nop nop nop nop address bank a , col b bank a , col n read t0 t1 t2 t3 t2n t4 t5 t1n t6 t6n t5n t wtr cl = 2 dq dqs dm di b do n t dqss (min) cl = 2 dq dqs dm di b do n t dqss (max) cl = 2 dq dqs dm di b do n don?t care transitioning data t dqss t dqss t dqss t3n
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 44 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 28: write-to-precharge ? uninterrupting notes: 1. di b = data-in for column b . 2. three subsequent elements of data-in are a pplied in the programmed order following di b . 3. an uninterrupted burst of 4 is shown. 4. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 5. the precharge and write commands are to the same device. however, the precharge and write commands may be to diff erent devices, in which case t wr is not required and the precharge command could be applied earlier. 6. a10 is low with the write comm and (auto precharge is disabled). 7. pre = precharge command. t dqss (nom) ck ck# command write nop nop nop pre 7 nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 t1n t6 t wr t rp dq dqs dm di b t dqss (min) dq dqs dm di b t dqss (max) dq dqs dm di b don?t care transitioning data t dqss t dqss t dqss
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 45 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 29: write-to-precharge ? interrupting notes: 1. di b = data-in for column b . 2. subsequent element of data-in is applied in the programmed order following di b . 3. an interrupted burst of 8 is show n; two data elements are written. 4. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 5. a10 is low with the write comm and (auto precharge is disabled). 6. dqs is required at t4 and t4n (nominal case) to register dm. 7. if the burst of 4 was used, dqs and dm wo uld not be required at t3, t3n, t4 and t4n. 8. pre = precharge command. t dqss t dqss (nom) ck ck# command write nop nop pre 8 nop nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 t1n t6 t wr t rp dq dqs dm di b t dqss t dqss (min) dq dqs dm di b t dqss t dqss (max) dq dqs dm di b don?t care transitioning data t3n t4n
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 46 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations figure 30: write-to-precharge ? odd number of data, interrupting notes: 1. di b = data-in for column b . 2. an interrupted burst of 8 is sh own; one data el ement is written. 3. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 4. a10 is low with the write comm and (auto precharge is disabled). 5. dqs is required at t4 and t4n (nominal case) to register dm. 6. if the burst of 4 was used, dqs and dm wo uld not be required at t3, t3n, t4 and t4n. 7. pre = precharge command. t dqss t dqss (nom) ck ck# command write nop nop pre 7 nop nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 t1n t6 t wr t rp dq dqs dm di b t dqss t dqss (min) dq dqs dm t dqss t dqss (max) dq dqs dm di b di b don?t care transitioning data t3n t4n
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 47 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations precharge the precharge command (figure 31) is used to deactivate the open row in a particu- lar bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been pre- charged, it is in the idle state and must be activated pr ior to any read or write com- mands being issued to that bank. figure 31: precharge command note: ba = bank address (if a10 is low; otherwise ?don?t care?). power-down (cke not active) unlike sdr sdrams, ddr sdrams require cke to be active at all time s an access is in progress, from the issuing of a read or wr ite command until completion of the access. thus a clock suspend is not supported. for reads, an access completion is defined when the read postamble is satisfied; for wr ites, an access completion is defined when the write recovery time ( t wr) is satisfied. power-down, as shown in figure 32 on page 48, is entered when cke is registered low and all table 8 (page 49) criteria are met. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referr ed to as active power-down. entering power- down deactivates the input and output buffer s, excluding ck, ck#, and cke. for maxi- mum power savings, the dll is frozen during precharge power-down mode. exiting cs # we# c a s # ra s # c ke a10 ba0,1 hi g h all bank s one bank ba a0?a9, a11, a12 c k c k# don ? t c are
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 48 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations power-down requires the device to be at the same voltage and frequency as when it entered power-down. however, power-down duration is limited by the refresh require- ments of the device ( t refc). while in power-down, cke low and a stable clock signal must be maintained at the inputs of the ddr sdram, while all other input signals are ?don?t care.? the power- down state is synchronously exited when cke is registered high (in conjunction with a nop or deselect command). a valid executable command may be applied one clock cycle later. figure 32: power-down t i s t i s no read/write a cc ess in pro g ress exit power- d own mo d e enter power- d own mo d e c ke c k c k# c ommand nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop valid t0 t1 t2 ta0 ta1 ta2 valid don ? t c are valid ta3
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 49 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations notes: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of com- mand n . 4. all states and sequences not shown are illegal or reserved. 5. cke must not drop low during a column acce ss. for a read, this means cke must stay high until after the r ead postamble time; for a write, cke must stay high until the write recovery time ( t wr) has been met. 6. once initialized, including during self refresh mode, v ref must be powered within the specified range. 7. upon exit of the self refresh mode the d ll is automatically enab led. a minimum of 200 clock cycles is needed before applying a read command for th e dll to lock. deselect or nop commands should be i ssued on any clock edge s occurring during the t xsnr period. table 8: truth table ? cke notes: 1?6 cke n-1 cke n current state command n action n notes l l power-down x maintain power-down self refresh x maintain self refresh l h power-down deselect or nop exit power-down self refresh deselect or nop exit self refresh 7 h l all banks idle deselect or nop precharge power-down entry bank(s) active deselect or nop active power-down entry all banks idle auto refresh self refresh entry h h see table 9 on page 50
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 50 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations notes: 1. this table applies when cke n -1 was high and cke n is high (see table 8 on page 49) and after t xsnr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where note d (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). exceptions are covered in the notes below. 3. current state definitions: ? idle: the bank has been precharged, and t rp has been met. ? row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regist er accesses are in progress. ? read: a read burst has been initiated, wi th auto precharge disabled, and has not yet terminated or been terminated. ? write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupt ed by a command issued to the same bank. command inhibit or nop command s, or allowable commands to the other bank should be issued on any clock edge occurring duri ng these states. allo wable commands to the other bank are determined by its current state and table 9 and according to table 10 on page 52. ? precharging: starts with re gistration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. ? row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the ?row active? state. ? read w/auto-precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. ? write w/auto-precharge enabled: starts with registration of a write command with auto precharge enab led and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be inte rrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. table 9: truth table ? current state bank n - command to bank n (notes: 1-6; notes appear below and on next page) current state cs# ras# cas# we# command/action notes any hx x x deselect (nop/continue previous operation) lhh h no operation (nop/continue previous operation) idle llh h active (select and activate row) ll l h auto refresh 7 ll l l load mode register 7 row active lh l h read (select column and start read burst) 10 lh l l write (select column and start write burst) 10 llh l precharge (deactivate row in bank or banks) 8 read (auto- precharge disabled) lh l h read (select column and start new read burst) 10 lh l l write (select column and start write burst) 10, 12 llh l precharge (truncate read burst, start precharge) 8 lhh l burst terminate 9 write (auto- precharge disabled) lh l h read (select column and start read burst) 10, 11 lh l l write (select column and start new write burst) 10 llh l precharge (truncate writ e burst, start precharge) 8, 11
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 51 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations ? refreshing: starts with registration of an auto refresh comma nd and ends when t rfc is met. once t rfc is met, the ddr sdram will be in the all banks idle state. ? accessing mode register: st arts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the ddr sdram will be in the all banks idle state. ? precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that all bank s are idle, and bursts are not in progress. 8. may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command/act ion column include reads or writes with auto precharge enabled and reads or wr ites with auto precharge disabled. 11. requires appropriate dm masking. 12. a write command may be appl ied after the completion of the read burst; otherwise, a burst terminate must be used to end the read burst prior to asserting a write com- mand.
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 52 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations notes: 1. this table applies when cke n -1 was high and cke n is high (see truth table 2) and after t xsnr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m , assuming that bank m is in such a state that the given command is allowable). exceptions are cov- ered in the notes below. 3. current state definitions: ? idle: the bank has been precharged, and t rp has been met. ? row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regist er accesses are in progress. ? read: a read burst has been initiated, wi th auto precharge disabled, and has not yet terminated or been terminated. ? write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated ? read with auto precharge enab led: see following text ? 3a ? write with auto precharge en abled: see following text ? 3a a. the read with auto precha rge enabled or write with au to precharge enabled states can each be broken into two parts: the ac cess period and the pr echarge period. for read with auto precharge, the precharge pe riod is defined as if the same burst was executed with auto precharg e disabled and then followed with the earliest possible precharge command that still accesses all of the data in the bu rst. for write with auto precharge, the precha rge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access pe riod starts with registration of the com- mand and ends where th e precharge period (or t rp) begins. table 10: truth table ? current state bank n - command to bank m notes: 1-6; notes appear below and on next page current state cs# ras# cas# we# command/action notes any hx x x deselect (nop/continue previous operation) lhh h no operation (nop/continue previous operation) idle xx x x any command otherwise allowed to bank m row activating, active, or precharging llhh active (select and activate row) lh l h read (select column and start read burst) 7 lh l l write (select column and start write burst) 7 llh l precharge read (auto- precharge disabled) llhh active (select and activate row) lh l h read (select column and start new read burst) 7 lh l l write (select column and start write burst) 7, 9 llh l precharge write (auto- precharge disabled) llhh active (select and activate row) lh l h read (select column and start read burst) 7, 8 lh l l write (select column and start new write burst) 7 llh l precharge read (with auto- precharge) llhh active (select and activate row) lh l h read (select column and start new read burst) 7, 3 lh l l write (select column and start write burst) 7, 9, 3 llh l precharge write (with auto- precharge) llhh active (select and activate row) lh l h read (select column and start read burst) 7, 3 lh l l write (select column and start new write burst) 7, 3 llh l precharge
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 53 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram operations this device supports concurre nt auto precharge such that when a read with auto precharge is enabled or a write with au to precharge is enabled any command to other banks is allowed, as long as that co mmand does not interrupt the read or write data transfer already in process. in either case, all other related limitations apply (e.g., contention between read data and write data must be avoided). b. the minimum delay from a read or write co mmand with auto prec harge enabled, to a command to a different bank is summarized below:. 4. auto refresh and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes listed in the command/act ion column include reads or writes with auto precharge enabled and reads or wr ites with auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be appl ied after the completion of the read burst; otherwise, a burst terminate must be used to end the read burst prior to asserting a write com- mand. table 11: command delays cl ru = cas latency (cl) rounded up to the next integer; bl = burst length from command to command minimum delay (with concurrent auto precharge) write w/ap read or read w/ap [1 + (bl/2)] t ck + t wtr write or write w/ap (bl/2) t ck precharge 1 t ck active 1 t ck read w/ap read or read w/ap (bl/2) t ck write or write w/ap [cl ru + (bl/2)] t ck precharge 1 t ck active 1 t ck
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 54 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications electrical specifications absolute maximum ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. table 12: absolute maximum ratings parameter absolute maximum value v dd supply voltage relative to vss -1v to +3.6v v dd q supply voltage relative to v ss -1v to +3.6v v ref and inputs voltage relative to v ss -1v to +3.6v i/o pins voltage relative to v ss -0.5v to v dd q +0.5v operating temperature, t a (ambient, commercial) 0c to +70c operating temperature, t a (ambient, industrial) - 40c to +85c storage temperature (plastic) -55c to +150c table 13: dc electrical characteristics and operating conditions (-6, -6t, -75e, -75z, -75) notes: 1?5, 16, notes appear on page 71?76; 0c t a +70c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v 36, 41 i/o supply voltage v dd q 2.3 2.7 v 36, 41 44 i/o reference voltage v ref 0.49 x v dd q 0.51 x v dd qv 6, 44 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v7, 44 input high (logic 1) voltage v ih ( dc )v ref + 0.15 v dd + 0.3 v28 input low (logic 0) voltage v il ( dc ) -0.3 v ref - 0.15 v28 input leakage current any input 0v v in v dd , v ref pin 0v v in 1.35v (all other pins not under test = 0v) i i -2 2 a output leakage current (dqs are disabled; 0v v out v dd q ) i oz -5 5 a output levels : full drive option - x4, x8, x16 high current (v out = v dd q - 0.373v, minimum v ref , minimum v tt ) i oh -16.8 ? ma 37, 39 low current (v out = 0.373v, maximum v ref , maximum v tt ) i ol 16.8 ? ma output levels : reduced drive option - x16 only high current (v out = v dd q - 0.763v, minimum v ref , minimum v tt ) i ohr -9 ? ma 38, 39 low current (v out = 0.763v, maximum v ref , maximum v tt ) i olr 9?ma
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 55 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications table 14: dc electrical characteristics and operating conditions (-5b ddr400) notes: 1?5, and 16;nnotes appear on page 71-76; 0c t a +70c; v dd q = +2.6v 0.1v, v dd = +2.6v 0.1v parameter/condition symbol min max units notes supply voltage v dd 2.5 2.7 v 36, 41, i/o supply voltage v dd q 2.5 2.7 v 36, 41 44, i/o reference voltage v ref 0.49 v dd q 0.51 v dd qv 6, 44 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v7, 44 input high (logic 1) voltage v ih ( dc )v ref + 0.15 v dd + 0.3 v28 input low (logic 0) voltage v il ( dc ) -0.3 v ref - 0.15 v28 input leakage current any input 0v v in v dd , v ref pin 0v v in 1.35v (all other pins not under test = 0v) i i -2 2 a output leakage current (dqs are disabled; 0v v out v dd q ) i oz -5 5 a output levels : full drive option - x4, x8, x16 high current (v out = v dd q - 0.373v, minimum v ref , minimum v tt ) i oh -16.8 - ma 37, 39 low current (v out = 0.373v, maximum v ref , maximum v tt ) i ol 16.8 - ma output levels : full drive option - x4, x8, x16 high current (v out = v dd q - 0.373v, minimum v ref , minimum v tt ) i ohr -9 - ma 38, 39 low current (v out = 0.763v, maximum v ref , maximum v tt ) i olr 9-ma table 15: ac input operating conditions 0c t a +70c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v (v dd q = +2.6v 0.1v, v dd = +2.6v 0.1v for ddr400) notes: 1?5, 14, 16; notes appear on page 71?76 parameter/condition symbol min max units notes input high (logic 1) voltage v ih ( ac )v ref + 0.310 ? v 14, 28, 40 input low (logic 0) voltage v il ( ac ) - v ref - 0.310 v 14, 28, 40 i/o reference voltage v ref ( ac ) 0.49 v dd q 0.51 v dd q v6
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 56 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications figure 33: input voltage waveform notes: 1. v oh (min) with test load is 1.927v 2. v ol (max) with test load is 0.373v 3. for non-ddr400 devices, numbers in diagra m reflect nomimal valu es utilizing circuit below. 0.940v 1.100v 1.200v 1.225v 1.250v 1.275v 1.300v 1.400v 1.5 6 0v v il (ac) v il (dc) v ref - a c noise v ref - d c error v ref + d c error v ref + a c noise re c eiver transmitter v ih( dc) v ih ( ac) v oh (min) ( 1 . 6 70v 1 for ss tl2 termination) v in ac - provi d e s margin b etween v ol (max) an d v il ac v ss q v dd q (2.3v minimum) v ol (max) (0. 8 3v 2 for ss tl2 termination) s ystem noise mar g in (power/ g roun d , c rosstalk, s i g nal inte g rity attenuation) referen c e point 25 25 v tt
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 57 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications figure 34: sstl_2 clock input notes: 1. this provides a minimum of 1.15v to a maximum of 1.35v, and is always half of v dd q. 2. ck and ck# must cross in this region. 3. ck and ck# must meet at least v id (dc) min when static and is centered around v mp (dc) 4. ck and ck# must have a mini mum 700mv peak to peak swing. 5. ck or ck# may not be more positive than v dd q + 0.3v or more nega tive than vss - 0.3v. 6. for ac operation, all dc clock requirements must also be satisfied. 7. numbers in diagram reflect no minal values non-ddr400 devices. table 16: clock input operating conditions 0c t a +70c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v (v dd q = +2.6v 0.1v, v dd = +2.6v 0.1v for ddr400) notes: 1?5, 15, 16, 30; no tes appear on page 71-76 parameter/condition symbol min max units notes clock input mid-point voltage; ck and ck# v mp ( dc ) 1.15 1.35 v 6, 9 clock input voltage level; ck and ck# v in ( dc ) -0.3 v dd q + 0.3 v6 clock input differential voltage; ck and ck# v id ( dc ) 0.36 v dd q + 0.6 v6, 8 clock input differential voltage; ck and ck# v id ( ac ) 0.7 v dd q + 0.6 v8 clock input crossing point voltage; ck and ck# v ix ( ac ) 0.5 v dd q - 0.2 0.5 v dd q + 0.2 v9 c k c k# 2.80v maximum c lo c k level 5 minimum c lo c k level 5 - 0.30v 1.25v 1.45v 1.05v v id (a c ) 4 v id (d c ) 3 x v mp (d c ) 1 v ix (a c ) 2 x
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 58 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications table 17: capacitance (x4, x8 tsop) note: 13; notes appear on page 71?76 parameter symbol min max units notes delta input/output capacitanc e: dq0-dq3 (x4), dq0-dq7 (x8) dc io ?0.50pf 24 delta input capacitance: command and address dc i 1 ?0.50pf 29 delta input capacitance: ck, ck# dc i 2 ?0.25pf 29 input/output capacitance: dqs, dqs, dm c io 4.0 5.0 pf input capacitance: command and address c i 1 2.0 3.0 pf input capacitance: ck, ck# c i 2 2.0 3.0 pf input capacitance: cke c i 3 2.0 3.0 pf table 18: capacitance (x4, x8 fbga) note: 13; notes appear on page 71?76 parameter symbol min max units notes delta input/output capa citance: dqs, dqs, dm dc io ?0.50pf 24 delta input capacitance: command and address dc i 1 ?0.50pf 29 delta input capacitance: ck, ck# dc i 2 ?0.25pf 29 input/output capacitance: dqs, dqs, dm c io 3.5 4.5 pf input capacitance: command and address c i 1 1.5 2.5 pf input capacitance: ck, ck# c i 2 1.5 2.5 pf input capacitance: cke c i 3 1.5 2.5 pf table 19: capacitance (x16 tsop) note: 13; notes appear on page 71?76 parameter symbol min max units notes delta input/output capacitance: dq0?dq7, ldqs, ldm dc iol ?0.50pf 24 delta input/output capacita nce: dq8?dq15, udqs, udm dc iou ?0.50pf 24 delta input capacitance: command and address dc i 1 ?0.50pf 29 delta input capacitance: ck, ck# dc i 2 ?0.25pf 29 input/output capacitance: dq, ldqs, udqs, ldm, udm c io 4.0 5.0 pf input capacitance: command and address c i 1 2.0 3.0 pf input capacitance: ck, ck# c i 2 2.0 3.0 pf input capacitance: cke c i 3 2.0 3.0 pf table 20: capacitance (x16 fbga) note: 13; notes appear on page 71?76 parameter symbol min max units notes delta input/output capacitance: dq0?dq7, ldqs, ldm dc iol ?0.50pf 24 delta input/output capacita nce: dq8?dq15, udqs, udm dc iou ?0.50pf 24 delta input capacitance: command and address dc i 1 ?0.50pf 29 delta input capacitance: ck, ck# dc i 2 ?0.25pf 29 input/output capacitance: dq, ldqs, udqs, ldm, udm c io 3.5 4.5 pf input capacitance: command and address c i 1 1.5 2.5 pf input capacitance: ck, ck# c i 2 1.5 2.5 pf input capacitance: cke c i 3 1.5 2.5 pf
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 59 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications table 21: i dd specifications and conditions (x4, x8; -5b) 0c t a +70c; v dd q = +2.6v 0.1v, v dd = +2.6v 0.1v notes: 1?5, 10, 12, 14, 46; notes appear on page 71?76; see also table 25 on page 63 parameter/condition symbol max units notes -5b operating current : one bank; active precharge; t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 155 ma 22, 47 operating current : one bank; active-read precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 185 ma 22, 47 precharge power-down standby current : all banks idle; power- down mode; t ck = t ck (min); cke = (low) i dd 2p 5 ma 23, 32, 49 idle standby current : cs# = high; all banks are idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs, and dm i dd 2f 55 ma 50 active power-down standby current : one bank active; power-down mode; t ck = t ck (min); cke = low i dd 3p 45 ma 23, 32, 49 active standby current : cs# = high; cke = high; one bank active ; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycl e; address and other control inputs changing once per clock cycle i dd 3n 60 ma 22 operating current : burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd 4r 190 ma 22, 47 operating current : burst = 2; writes ; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 195 ma 22 auto refresh burst current : t refc = t rfc (min) i dd 5 345 ma 49 t refc = 7.8s i dd 5a 11 ma 27, 49 self refresh current : cke 0.2v standard i dd 6 5ma11 low power (l) i dd 6a 3ma11 operating current : four bank interleaving reads (burst = 4) with auto precharge, t rc = minimum t rc allowed; t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 450 ma 22, 48
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 60 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications table 22: i dd specifications and conditions (x4, x8; -6/-6t/-75e/-75z/-75) 0c t a +70c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v notes: 1?5, 10, 12, 14, 46; notes appear on page 71?76; see also table 25 on page 63 parameter/condition symbol max units notes -6/6t -75e -75z/-75 operating current : one bank; active precharge; t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 130 130 115 ma 22, 47 operating current : one bank; active-read precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 160 160 145 ma 22, 47 precharge power-down standby current : all banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd 2p 5 5 5 ma 23, 32, 49 idle standby current : cs# = high; all banks are idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs, and dm i dd 2f 45 45 40 ma 50 active power-down standby current : one bank active; power-down mode; t ck = t ck (min); cke = low i dd 3p 35 35 30 ma 23, 32, 49 active standby current : cs# = high; cke = high; one bank active ; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 50 50 45 ma 22 operating current : burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd 4r 165 165 145 ma 22, 47 operating current : burst = 2; writes ; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 175 155 135 ma 22 auto refresh burst current : t refc = t rfc (min) i dd 5 290 290 280 ma 49 t refc = 7.8s i dd 5a 10 10 10 ma 27, 49 self refresh current : cke 0.2v standard i dd 6 55 5ma11 low power (l) i dd 6a 33 3ma11 operating current : four bank interleaving reads (burst = 4) with auto precharge, t rc = minimum t rc allowed; t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 405 400 350 ma 22, 48
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 61 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications table 23: i dd specifications and conditions (x16; -5b) 0c t a +70c; v dd q = +2.6v 0.1v, v dd = +2.6v 0.1v notes: 1?5, 10, 12, 14, 46; notes appear on page 71?76; see also table 25 on page 63 parameter/condition symbol max units notes -5b operating current : one bank; active precharge; t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 155 ma 22, 47 operating current : one bank; active-read precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 195 ma 22, 47 precharge power-down standby current : all banks idle; power- down mode; t ck = t ck (min); cke = (low) i dd 2p 5ma23, 32, 49 idle standby current : cs# = high; all banks are idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs, and dm i dd 2f 55 ma 50 active power-down standby current : one bank active; power-down mode; t ck = t ck (min); cke = low i dd 3p 45 ma 23, 32, 49 active standby current : cs# = high; cke = high; one bank active ; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 60 ma 22 operating current : burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd 4r 210 ma 22, 47 operating current : burst = 2; writes ; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 215 ma 22 auto refresh burst current : t refc = t rfc(min) i dd 5 345 ma 49 t refc = 7.8s i dd 5a 11 ma 27, 49 self refresh current : cke 0.2v standard i dd 6 6ma11 low power (l) i dd 6a 4ma11 operating current : four bank interleaving reads (burst = 4) with auto precharge, t rc = minimum t rc allowed; t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 480 ma 22, 48
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 62 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications table 24: i dd specifications and conditio ns (x16; -6/-6t/-75e/-75z/-75) 0c t a +70c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v notes: 1?5, 10, 12, 14, 46; notes appear on page 71?76; see also table 25 on page 63 parameter/condition symbol max units notes -6/6t -75e -75z/-75 operating current : one bank; active precharge; t rc = t rc (min); t ck = t ck (min); dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 130 130 115 ma 22, 47 operating current : one bank; active-read precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 160 160 145 ma 22, 47 precharge power-down standby current : all banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd 2p 5 5 5 ma 23, 32, 49 idle standby current : cs# = high; all banks are idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs, and dm i dd 2f 45 45 40 ma 50 active power-down standby current : one bank active; power-down mode; t ck = t ck (min); cke = low i dd 3p 35 35 30 ma 23, 32, 49 active standby current : cs# = high; cke = high; one bank active ; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n 50 50 45 ma 22 operating current : burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd 4r 165 165 145 ma 22, 47 operating current : burst = 2; writes ; continuous burst; one bank active; address and contro l inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 195 160 135 ma 22 auto refresh burst current : t refc = t rfc (min) i dd 5 290 290 280 ma 49 t refc= 7.8s i dd 5a 10 10 10 ma 27, 49 self refresh current : cke 0.2v standard i dd 6 55 5ma11 low power (l) i dd 6a 33 3ma11 operating current : four bank interleaving reads (burst = 4) with auto precharge, t rc = minimum t rc allowed; t ck = t ck (min); address and control inputs change only during active read or write commands i dd 7 405 400 350 ma 22, 48
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 63 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications table 25: i dd test cycle times values reflect number of clock cycles for each test i dd test speed grade clock cycle time t rrd t rcd t ras t rp t rc t rfc t refi cl i dd 0 -75/75z 7.5ns na na 6 3 9 na na na -75e 7.5ns na na 6 2 8 na na na -6/-6t 6ns na na 7 3 10 na na na -5b 5ns na na 8 3 11 na na na i dd 1 -75 7.5ns na na 6 3 9 na na 2.5 -75z 7.5ns na na 6 3 9 na na 2 -75e 7.5ns na na 6 2 8 na na 2 -6/-6t 6ns na na 7 3 10 na na 2.5 -5b 5ns na na na na na na na 3 i dd 4r -75 7.5ns na na na na na na na 2.5 -75z 7.5ns na na na na na na na 2 -75e 7.5ns na na na na na na na 2 -6/-6t 6ns na na na na na na na 2.5 -5b 5ns na na na na na na na 3 i dd 4w -75 7.5ns na na na na na na na na -75z 7.5ns na na na na na na na na -75e 7.5ns na na na na na na na na -6/-6t 6ns na na na na na na na na -5b 5ns na na na na na na na na i dd 5 -75/75z 7.5ns na na na na na 10 10 na -75e 7.5ns na na na na na 9 9 na -6/-6t 6ns na na na na na 12 12 na -5b 5ns na na na na na 14 14 na i dd 5a -75/75z 7.5ns na na na na na 10 1,029 na -75e 7.5ns na na na na na 10 1,029 na -6/-6t 6ns na na na na na 12 1,288 na -5b 5ns na na na na na 14 1,546 na i dd 7 -75 7.5ns 2/4 3 na 3 10 na na 2.5 -75z 7.5ns 2/4 3 na 3 10 na na 2 -75e 7.5ns 2 3 na 2 8 na na 2 -6/-6t 6ns 2/4 3 na 3 10 na na 2.5 -5b 5ns 2/4 3 na 3 11 na na 3
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 64 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications table 26: electrical characteristics & reco mmended ac operating conditions (-5b) notes: 1?5, 14?17, 33; note s appear on page 71?76; 0c t a +70c; v dd q = +2.6v 0.1v, v dd = +2.6v 0.1v ac characteristics -5b units notes parameter symbol min max access window of dq from ck/ck# t ac -0.70 +0.70 ns ck high-level width t ch 0.45 0.55 t ck 30 ck low-level width t cl 0.45 0.55 t ck 30 clock cycle time cl = 3 t ck (3) 5 7.5 ns 51 cl = 2.5 t ck (2.5) 6 13 ns 45, 51 cl = 2 t ck (2) 7.5 13 ns 45, 51 dq and dm input hold time relative to dqs t dh 0.40 ns 26, 31 dq and dm input setup time relative to dqs t ds 0.40 ns 26, 31 dq and dm input pulse width (for each input) t dipw 1.75 ns 31 access window of dqs from ck/ck# t dqsck -0.60 +0.60 ns dqs input high pulse width t dqsh 0.35 t ck dqs input low pulse width t dqsl 0.35 t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq 0.40 ns 25, 26 write command to first dqs latching transition t dqss 0.72 1.28 t ck dqs falling edge to ck rising ? setup time t dss 0.2 t ck dqs falling edge from ck rising ? hold time t dsh 0.2 t ck half-clock period t hp t ch, t cl ns 34 data-out high-z window from ck/ck# t hz +0.70 ns 18,42 data-out low-z window from ck/ck# t lz -0.70 ns 18,42 address and control input hold time (slew rate 0.5 v/ns) t ih f 0.60 ns 14 address and control input setup time (slew rate 0.5 v/ns) t is f 0.60 ns 14 address and control input pulse width (for each input) t ipw 2.2 ns load mode register command cycle time t mrd 10 ns dq?dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs ns 25, 26 data hold skew factor t qhs 0.50 ns active-to-precharge command t ras 40 70,000 ns 35 active-to-read with auto precharge command t rap 15 ns active-to-active/auto refresh command period t rc 55 ns auto refresh command period t rfc 70 ns 49 active-to-read or write delay t rcd 15 ns precharge command period t rp 15 ns dqs read preamble t rpre 0.9 1.1 t ck 43 dqs read postamble t rpst 0.4 0.6 t ck 43 active bank a to active bank b command t rrd 10 ns dqs write preamble t wpre 0.25 t ck dqs write preamble setup time t wpres 0 ns 20, 21 dqs write postamble t wpst 0.4 0.6 t ck 19 write recovery time t wr 15 ns internal write-to-read command delay t wtr 2 t ck data valid output window (dvw) n/a t qh - t dqsq ns 25 refresh-to-refresh command interval t refc 70.3 s 23 average periodic refresh interval t refi 7.8 s 23
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 65 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications terminating voltage delay to v dd t vtd 0 ns exit self refresh-to-non-read command t xsnr 70 ns exit self refresh-to-read command t xsrd 200 t ck table 26: electrical characteristics & reco mmended ac operating conditions (-5b) notes: 1?5, 14?17, 33; note s appear on page 71?76; 0c t a +70c; v dd q = +2.6v 0.1v, v dd = +2.6v 0.1v ac characteristics -5b units notes parameter symbol min max
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 66 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications table 27: electrical characteristics and recommen ded ac operating conditions (-6/-6t/-75e) notes: 1?5, 14?17, 33; note s appear on page 71?76; 0c t a +70c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v ac characteristics -6 (fbga) -6t (tsop) -75e units notes parameter symbol min max min max min max access window of dq from ck/ck# t ac -0.70 +0.70 -0.70 +0.70 -0.75 +0.75 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck 30 ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 30 clock cycle time cl = 2.5 t ck (2.5) 6 13 6 13 7.5 13 ns 45, 51 cl = 2 t ck (2) 7.5 13 7.5 13 7.5 13 ns 45, 51 dq and dm input hold time relative to dqs t dh 0.45 0.45 0.5 ns 26, 31 dq and dm input setup time relative to dqs t ds 0.45 0.45 0.5 ns 26, 31 dq and dm input pulse width (for each input) t dipw 1.75 1.75 1.75 ns 31 access window of dqs from ck/ck# t dqsck -0.6 +0.6 -0.6 +0.6 -0.75 +0.75 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.4 0.45 0.5 ns 25, 26 write command-to-first dq s latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 0.2 t ck half-clock period t hp t ch, t cl t ch, t cl t ch, t cl ns 34 data-out high-z window from ck/ck# t hz +0.7 +0.7 +0.75 ns 18, 42 data-out low-z window from ck/ck# t lz -0.7 -0.7 -0.75 ns 18, 42 address and control input ho ld time (fast slew rate) t ih f .75 .75 .90 ns address and control input se tup time (fast slew rate) t is f .75 .75 .90 ns address and control input ho ld time (slow slew rate) t ih s 0.8 0.8 1 ns 14 address and control input setup time (slow slew rate) t is s 0.8 0.8 1 ns 14 address and control input pulse width (for each input) t ipw 2.2 2.2 2.2 ns load mode register command cycle time t mrd 12 12 15 ns dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs t hp - t qhs ns 25, 26 data hold skew factor t qhs 0.50 0.55 0.75 ns active-to-precharge command t ras 42 70,00 0 42 70,00 0 40 120,00 0 ns 35, 53 active-to-read with auto precharge command t rap 15 15 15 ns active-to-active/auto refresh command period t rc 60 60 60 ns auto refresh command period t rfc 72 72 75 ns 49 active-to-read or write delay t rcd 15 15 15 ns precharge command period t rp 15 15 15 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck 43 dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 43 active bank a to active bank b command t rrd 12 12 15 ns dqs write preamble t wpre 0.25 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 0 ns 20, 21 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 19
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 67 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications write recovery time t wr 15 15 15 ns internal write-to-read command delay t wtr 1 1 1 t ck data valid output window (dvw) n/a t qh - t dqsq t qh - t dqsq t qh - t dqsq ns 25 refresh-to-refresh command interval t refc 70.3 70.3 70.3 s 23 average periodic refresh interval t refi 7.8 7.8 7.8 s 23 terminating voltage delay to v dd t vtd 0 0 0 ns exit self refresh-to-non-read command t xsnr 75 75 75 ns exit self refresh-to-read command t xsrd 200 200 200 t ck table 27: electrical characteristics and recommen ded ac operating conditions (-6/-6t/-75e) notes: 1?5, 14?17, 33; note s appear on page 71?76; 0c t a +70c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v ac characteristics -6 (fbga) -6t (tsop) -75e units notes parameter symbol min max min max min max
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 68 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications table 28: electrical characteristics and reco mmended ac operating conditions (-75z/-75) notes: 1?5, 14?17, 33; note s appear on page 71?76; 0c t a +70c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v ac characteristics -75z -75 units notes parameter symbol min max min max access window of dq from ck/ck# t ac -0.75 +0.75 -0.75 +0.75 ns ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 30 ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 30 clock cycle time cl = 2.5 t ck (2.5) 7.5 13 7.5 13 ns 45, cl = 2 t ck (2) 7.5 13 10 13 ns 45, dq and dm input hold time relative to dqs t dh 0.5 0.5 ns 26, 31 dq and dm input setup time relative to dqs t ds 0.5 0.5 ns 26, 31 dq and dm input pulse width (for each input) t dipw 1.75 1.75 ns 31 access window of dqs from ck/ck# t dqsck -0.75 +0.75 -0.75 +0.75 ns dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.5 0.5 ns 25, 26 write command-to-first dq s latching transition t dqss 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 t ck half-clock period t hp t ch, t cl t ch, t cl ns 34 data-out high-z window from ck/ck# t hz +0.75 +0.75 ns 18, 42 data-out low-z window from ck/ck# t lz -0.75 -0.75 ns 18, 42 address and control input ho ld time (fast slew rate) t ih f .90 .90 ns address and control input se tup time (fast slew rate) t is f .90 .90 ns address and control input ho ld time (slow slew rate) t ih s 11 ns14 address and control input se tup time (slow slew rate) t is s 11 ns14 address and control input pulse width (for each input) t ipw 2.2 2.2 ns load mode register command cycle time t mrd 15 15 ns dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs ns 25, 26 data hold skew factor t qhs 0.75 0.75 ns active-to-precharge command t ras 40 120,000 40 120,000 ns 35 active-to-read with auto precharge command t rap 20 20 ns active-to-active/auto refresh command period t rc 65 65 ns auto refresh command period t rfc 75 75 ns 49 active-to-read or write delay t rcd 20 20 ns precharge command period t rp 20 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck 43 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck 43 active bank a to active bank b command t rrd 15 15 ns dqs write preamble t wpre 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 ns 20, 21 dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 19 write recovery time t wr 15 15 ns internal write-to-read command delay t wtr 1 1 t ck data valid output window (dvw) n/a t qh - t dqsq t qh - t dqsq ns 25 refresh-to-refresh command interval t refc 70.3 70.3 s 23
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 69 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications average periodic refresh interval t refi 7.8 7.8 s 23 terminating voltage delay to v dd t vtd 0 0 ns exit self refresh-to-non-read command t xsnr 75 75 ns exit self refresh-to-read command t xsrd 200 200 t ck table 28: electrical characteristics and reco mmended ac operating conditions (-75z/-75) notes: 1?5, 14?17, 33; note s appear on page 71?76; 0c t a +70c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v ac characteristics -75z -75 units notes parameter symbol min max min max
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 70 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram electrical specifications table 29: input slew rate derating values for addresses and commands notes: 14; notes appear on page 71?76; 0c t a +70c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v speed slew rate t is t ih units -75/-75z/-75e 0.500v / ns 1.00 1 ns -75/-75z/-75e 0.400v / ns 1.05 1 ns -75/-75z/-75e 0.300v / ns 1.15 1 ns table 30: input slew rate derating values for dq, dqs, and dm notes: 31; notes appear on page 71-76; 0c t a +70c; v dd q = +2.5v 0.2v, v dd = +2.5v 0.2v speed slew rate t ds t dh units -75/-75z/-75e 0.500v / ns 0.50 0.50 ns -75/-75z/-75e 0.400v / ns 0.55 0.55 ns -75/-75z/-75e 0.300v / ns 0.60 0.60 ns
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 71 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram notes notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc ch aracteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs (except for i dd measurements) measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environ- ment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1v/ns in the range between v il ( ac ) and v ih ( ac ). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as th e signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v dd q/2 of the transmitting device and to track variations in the dc level of the same. peak-to- peak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v dd q/2, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 9. the value of v ix and v mp are expected to equal v dd q/2 of the transmitting device and must track variations in the dc level of the same. 10. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle times at cl = 3 for -5b, cl = 2.5 for -6/-6t/-75, and cl = 2 for - 75e/-75z speeds with the outputs open. 11. enables on-chip refresh and address counters. 12. i dd specifications are tested afte r the device is properly initialized, and is averaged at the defined cycle rate. 13. this parameter is sampled. v dd = +2.5v 0.2v, v dd q = +2.5v 0.2v, v ref = v ss , f = 100 mhz, t a = 25c, v out (dc) = v dd q/2, v out (peak-to-peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in loading. 14. for slew rates less than 1v/ns and greater than or equal to 0.5v/ns. if the slew rate is less than 0.5v/ns, timing must be derated: t is has an additional 50ps per each 100mv/ ns reduction in slew rate from the 500mv/ns. t ih has 0ps added, that is, it remains constant. if the slew rate exceeds 4.5v/ns, functionality is uncertain. for -5b, -6, and -6t, slew rates must be greater than or equal to 0.5v/ns. 15. the ck/ck# input reference level (for timi ng referenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . output (v out ) reference point 50 v tt 30pf
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 72 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram notes 16. inputs are not recognized as valid until v ref stabilizes. once initialized, including self refresh mode, v ref must be powered within specified range. exception: during the period before v ref stabilizes, cke < 0.3 v dd q is recognized as low. 17. the output timing referenc e level, as measured at the timing reference point (indi- cated in note 3) is v tt . 18. t hz and t lz transitions occur in the same access time windows as data valid transi- tions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 19. the intent of the ?don?t care? state af ter completion of the postamble is the dqs- driven signal should either be high, low, or high-z, and that any signal transition within the input switching region must follow valid input requirements. that is, if dqs transitions high (above v ih dc (min) then it must not transition low (below v ih ( dc ) prior to t dqsh (min). 20. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. it is recommended that dqs be valid (high or low) on or before the write com- mand. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 22. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd measure- ments is the largest multiple of t ck that meets the maximum absolute value for t ras. 23. the refresh period is 64ms. this equates to an average refresh rate of 7.8125s. how- ever, an auto refresh command must be as serted at least once every 70.3s; burst refreshing or posting by the dram controll er greater than 8 refresh cycles is not allowed. 24. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device. 25. the data valid window is derived by achieving other specifications - t hp ( t ck/2), t dqsq, and t qh ( t qh = t hp - t qhs). the data valid window derates in direct propor- tion to the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle vari ation of 45/55, because functionality is uncertain when operating beyond a 45/55 ratio. the data valid window derating curves are provided in figure 35 on page 73 for duty cycles ranging between 50/50 and 45/55. 26. referenced to each output group: x4 = dqs with dq0?dq3; x8 = dqs with dq0?dq7; x16 = ldqs with dq0?dq7; and udqs with dq8?dq15. 27. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period ( t rfc [min]) else cke is low (i.e., during standby). 28. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through to the target ac level, v il (ac) or v ih (ac). b. reach at least the target ac level. c. after the ac target level is reached, cont inue to maintain at least the target dc level, v il (dc) or v ih (dc). 29. the input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. ck and ck# input slew rate must be 1v/ns ( 2v/ns if measured differentially).
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 73 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram notes figure 35: derating data valid window ( t qh - t dqsq) 31. dq and dm input slew rates must not deviate from dqs by more than 10 percent. if the dq/dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. for -5b, -6 and -6t speed grades, slew rate must be 0.5v/ns. if slew rate exce eds 4v/ns, functionality is uncertain. 32. v dd must not vary more than 4 percent if ck e is not active while any bank is active. 33. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. 34. t hp (min) is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs, coll ectively, during bank active. 35. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satisfied prior to the internal precharge command being issued. 36. any positive glitch must be less than 1/ 3 of the clock cycle and not more than +400mv or 2.9v (+300mv or 2.9v maximum for -5b) , whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mv or 2.2v (2.4v for -5b), whichever is more positive. the average cannot be below the +2.5v (2.6v for -5b) minimum. 37. normal output drive curves: a. the full driver pull-down current variation from min to max process, tempera- ture and voltage will lie within the outer bounding lines of the v-i curve of figure 36 on page 74. b. the driver pull-down current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 36 on page 74. c. the full driver pull-up current variation from min to max process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure 37 on page 74. 3.0ns 2.5ns 2.0ns 1.5ns 1.0ns 50/50 49/51 48/53 46/54 47/53 45/55 -6t @ t ck = 7.5ns -75e / -75 @ t ck = 7.5ns -6 @ t ck = 6ns -6t @ t ck = 6ns -5b @ t ck = 5ns 1.48 1.45 1.43 1.40 1.38 1.35 2.75 2.60 2.56 2.53 2.45 2.41 2.38 2.68 2.35 2.31 2.28 2.13 2.20 2.16 2.43 2.10 2.07 2.04 1.89 1.86 1.83 1.80 1.98 1.95 2.00 1.97 1.94 1.91 1.88 1.73 1.70 1.82 1.79 1.58 1.55 clock duty cycle data valid window 2.71 2.46 1.53 2.64 2.39 1.92 1.76 1.85 1.60 1.50 2.49 2.50 2.24 2.01
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 74 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram notes d. the driver pull-up current variation within nominal limits of voltage and temper- ature is expected, but not guaranteed, to li e within the inner bounding lines of the v-i curve of figure 37 on page 74. e. the full ratio variation of max to min pull-up and pull-down current should be between 0.71 and 1.4, for drain-to-source vo ltages from 0.1v to 1.0v at the same voltage and temperature. f. the full ratio variation of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to -source voltages from 0.1v to 1.0v. figure 36: full drive pull-down characteristics figure 37: full drive pull-up characteristics 38. reduced output drive curves: a. the full driver pull-down current variation from min to max process, tempera- ture, and voltage will lie within the outer bounding lines of the v-i curve of figure 38 on page 75. b. the driver pull-down current variation, within nominalvoltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 38 on page 75. 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 v out (v) i out (ma) -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.0 0.5 1.0 1.5 2.0 2.5 i out (ma) v dd q - v out (v)
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 75 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram notes c. the full driver pull-up current variation from min to max process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure 39. d. the driver pull-up current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 39 on page 75. e. the full ratio variation of the max to min pull-up and pull-down current should be between 0.71 and 1.4 for device drain-to -source voltages from 0.1v to 1.0v at the same voltage and temperature. f. the full ratio variation of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to -source voltages from 0.1v to 1.0v. figure 38: reduced drive pull-down characteristics figure 39: reduced drive pull-up characteristics 39. the voltage levels used are derived from a minimum v dd level and the referenced test load. in practice, the voltage levels obtained from a properly terminated bus will pro- vide significantly different voltage values. 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 v out (v) i out (ma) -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.0 0.5 1.0 1.5 2.0 2.5 i out (ma) v dd q - v out (v)
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 76 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram notes 40. v ih overshoot: v ih (max) = v dd q + 1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. vil undershoot: vil (min) = -1.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 41. v dd and v dd q must track each other. 42. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + t rpre (max) condition. 43. t rpst end point and t rpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving ( t rpst), or begins driving ( t rpre). 44. during initialization, v dd q, v tt , and vref must be equal to or less than v dd + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v dd /v dd q are 0v, provided a minimum of 42 of series resistance is used between the v tt supply and the input pin. 45. the current micron part operates below 83 mhz (slowest specified jedec operating frequency). as such, future die may not reflect this option. 46. when an input signal is high or low, it is defined as a steady state logic high or low. 47. random addressing changing 50 percent of data changing at every transfer. 48. random addressing changing 100 percen t of data changing at every transfer. 49. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refres h command is registered, cke must be active at each risi ng clock edge, until t rfc has been satisfied. 50. i dd 2n specifies the dq, dqs, and dm to be driven to a valid high or low logic level. i dd 2q is similar to i dd 2f except i dd 2q specifies the address and control inputs to remain stable. although i dd 2f, i dd 2n, and i dd 2q are similar, i dd 2f is ?worst case.? 51. whenever the operating frequency is altered, not including jitter, the dll is required to be reset followed by 200 clock cycles before any read command. 52. this is the dc voltage supplied at the dram and is inclusive of all noise up to 20mhz. any noise above 20 mhzat the dram generated from any source other than that of the dram itself may not exceed th e dc voltage range of 2.6v 100mv. 53. the -6/-6t speed grades will operate with t ras (min) = 40ns and t ras (max) = 120,000ns at any slower frequency.
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 77 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram notes note: the above characteristics are specified un der best, worst, and no minal process variation/ conditions. table 31: normal output drive characteristics voltage (v) pull-down current (ma) pull-up current (ma) nominal low nominal high minimum maximum nominal low nominal high minimum maximum 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10.0 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20.0 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 - 50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 - 51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 - 51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 - 51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 - 51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 - 51.6 -124.0 -40.5 -156.9 2.1 62.8 99.1 49.6 126.5 - 51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 78 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram notes note: the above characteristics are specified un der best, worst, and no minal process variation/ conditions. table 32: reduced output drive characteristics voltage (v) pull-down current (ma) pull-up current (ma) nominal low nominal high minimum maximum nominal low nominal high minimum maximum 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -7.8 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.9 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 79 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram notes figure 40: x4, x8 data output timing ? t dqsq, t qh, and data valid window notes: 1. dq transitioning af ter dqs transition define t dqsq window. dqs transitions at t2 and at t2n are an ?early dqs,? at t3 is a ?nominal dqs,? an d at t3n is a ?late dqs.? 2. for a x4, only two dq apply. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transition and ends with the last valid dq transition. 4. t qh is derived from t hp: t qh = t hp - t qhs. 5. t hp is the lesser of t cl or t ch clock transition collectively when a bank is active. 6. the data valid window is derived for each dqs transitions and is defined as t qh minus t dqsq. dq (last d ata vali d ) dq 2 dq 2 dq 2 dq 2 dq 2 dq 2 dq s 1 dq (last d ata vali d ) dq (first d ata no lon g er vali d ) dq (first d ata no lon g er vali d ) all dq an d dq s , c olle c tively 6 earliest si g nal transition latest si g nal transition t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n c k c k# t1 t2 t3 t4 t2n t3n t qh 4 t hp 5 t hp 5 t hp 5 t qh 4 t qh 4 t hp 5 t hp 5 t hp 5 t qh 4 t dq s q 3 t dq s q 3 t dq s q 3 t dq s q 3 data vali d win d ow data vali d win d ow data vali d win d ow data vali d win d ow
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 80 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram notes figure 41: x16 data output timing ? t dqsq, t qh, and data valid window notes: 1. dq transitioning a fter dqs transition define t dqsq window. ldqs defines the lower byte and udqs defines the upper byte. 2. dq0, dq1, dq2, dq3, dq4, dq5, dq6, or dq7. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transition and ends with the last valid dq transition. 4. t qh is derived from t hp: t qh = t hp - t qhs. 5. t hp is the lesser of t cl or t ch clock transition collectively when a bank is active. 6. the data valid window is derive d for each dqs transition and is t qh minus t dqsq. 7. dq8, dq9, dq10, d11, dq12, dq13, dq14, or dq15. dq (last d ata vali d ) 2 dq 2 dq 2 dq 2 dq 2 dq 2 dq 2 ldq s 1 dq (last d ata vali d ) 2 dq (first d ata no lon g er vali d ) 2 dq (first d ata no lon g er vali d ) 2 dq0 - dq7 an d ldq s , c olle c tively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n c k c k# t1 t2 t3 t4 t2n t3n t qh 4 t qh 4 t dq s q 3 t dq s q 3 t dq s q 3 t dq s q 3 data vali d win d ow data vali d win d ow dq (last d ata vali d ) 7 dq 7 dq 7 dq 7 dq 7 dq 7 dq 7 udq s 1 dq (last d ata vali d ) 7 dq (first d ata no lon g er vali d ) 7 dq (first d ata no lon g er vali d ) 7 dq8?dq15 an d udq s , c olle c tively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n t qh 4 t qh 4 t qh 4 t qh 4 t dq s q 3 t dq s q 3 t dq s q 3 t dq s q 3 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t qh 4 t qh 4 data vali d win d ow data vali d win d ow data vali d win d ow data vali d win d ow data vali d win d ow upper byte lower byte data vali d win d ow
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 81 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram notes figure 42: data output timing ? t ac and t dqsck notes: 1. t dqsck is the dqs output window relative to ck and is the ?lon g term? component of dqs skew. 2. dq transitioning after dqs transition define t dqsq window. 3. all dq must transition by t dqsq after dqs transitions, regardless of t ac. 4. t ac is the dq output window relative to ck, and is the ?lon g term? component of dq skew. 5. t lz (min) and t ac (min) are the first valid signal transition. 6. t hz (max), and t ac (max) are the latest valid signal transition. 7. read command with cl = 2 issued at t0. figure 43: data input timing notes: 1. t dsh (min) generally occurs during t dqss (min). 2. t dss (min) generally occurs during t dqss (max). 3. write command issued at t0. 4. for x16, ldqs controls the lower byte and udqs controls the upper byte. ck ck# dqs, or ldqs/udqs 2 t0 7 t1 t2 t3 t4 t5 t2n t3n t4n t5n t6 t rpst t lz (min) t dqsck 1 (max) t dqsck 1 (min) t dqsck 1 (max) t dqsck 1 (min) t hz(max) t rpre dq (last data valid) dq (first data valid) all dq values, collectively 3 t ac 4 (min) t ac 4 (max) t lz (min) t hz (max) t2 t2 t2n t3n t4n t5n t2n t2n t3n t3n t4n t4n t5n t5n t3 t4 t4 t5 t5 t2 t3 t4 t5 t3 dqs t dqss t dqsh t wpst t dh t ds t dqsl t dss 2 t dsh 1 t dsh 1 t dss 2 dm dq ck ck# t0 3 t1 t1n t2 t2n t3 di b don?t care transitioning data t wpre t wpres
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 82 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram initialization initialization to ensure device operation the dram mu st be initialized as described below: 1. simultaneously apply power to v dd and v dd q. 2. apply v ref and then v tt power. 3. assert and hold cke at a lvcmos logic low. 4. provide stable clock signals. 5. wait at least 200s. 6. bring cke high and provide at least one nop or deselect command. at this point the cke input changes from a lvcmos input to a sstl2 input only and will remain a sstl_2 input unless a power cycle occurs. 7. perform a precharge all command. 8. wait at least t rp time, during this time nops or deselect commands must be given. 9. using the lmr command program the extended mode register (e0 = 0 to enable the dll and e1 = 0 for normal drive or e1 = 1 fo r reduced drive, e2 through en must be set to 0; where n = most significant bit). 10. wait at least t mrd time, only nops or deselect commands are allowed. 11. using the lmr command program the mode register to set operating parameters and to reset the dll. at least 200 clock cycles are required between a dll reset and any read command. 12. wait at least t mrd time, only nops or deselect commands are allowed. 13. issue a precharge all command. 14. wait at least t rp time, only nops or deselect commands are allowed. 15. issue an auto refresh command. this may be moved prior to step 13. 16. wait at least t rfc time, only nops or deselect commands are allowed. 17. issue an auto refresh command. this may be moved prior to step 13. 18. wait at least t rfc time, only nops or deselect commands are allowed. 19. although not required by the micron device, jedec requires a lmr command to clear the dll bit (set m8 = 0). if a lmr command is issued the same operating parameters should be utilized as in step 11. 20. wait at least t mrd time, only nops or deselect commands are allowed. 21. at this point the dram is ready for any va lid command. at least 200 clock cycles with cke high are required between step 11 (dll reset) and any read command.
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 83 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram initialization figure 44: initialization flow diagram v dd an d v dd q ramp apply v ref an d v tt c ke must b e lv c mo s low apply sta b le c lo c ks brin g c ke hi g h with a nop c omman d wait at least 200us pre c har g e all assert nop or de s ele c t for t rp time c onfi g ure exten d e d mo d e re g ister c onfi g ure loa d mo d e re g ister an d reset dll assert nop or de s ele c t for t mrd time assert nop or de s ele c t for t mrd time pre c har g e all issue auto refre s h c omman d assert nop or de s ele c t for t rf c time optional lmr c omman d to c lear dll b it assert nop or de s ele c t for t mrd time dram is rea d y for any vali d c omman d s tep 1 2 3 4 5 6 7 8 9 1 0 11 1 2 1 3 1 4 1 5 16 1 7 18 1 9 20 2 1 assert nop or de s ele c t c omman d s for t rf c issue auto refre s h c omman d assert nop or de s ele c t for t rp time
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 84 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram timing diagrams timing diagrams figure 45: initialize and load mode registers notes: 1. v tt is not applied directly to the device; however, t vtd should be greater th an or equal to zero to avoid device latch-up. v dd q, v tt , and v ref , must be equal to or less than v dd + 0.3v. alterna- tively, v tt may be 1.35v maximum during power up, even if v dd /v dd q are 0v, provided a mini- mum of 42 ohms of series re sistance is used between the v tt supply and the input pin. once initialized, v ref must always be powered with in specified range. 2. reset the dll with a8 = h while programming the operating parameters. 3. t mrd is required before any command can be applied (during mrd time only nops or deselects are allowed), and 200 cycles of ck are required before a read command can be issued. 4. the two auto refresh commands at td0 and te0 may be applied following the load mode register (lmr ) command at ta0. 5. although not required by the micron device, jedec specifies issuing another lmr command (a8 = l) prior to activating any bank. if another lmr command is issued, the same operating param- eters, previously issued, must be used. 6. pre = precharge command, lmr = load mode register command, ar = auto refresh command, act = active command, ra = row address, ba = bank address. t vtd 1 cke lvcmos low level dq ba0, ba1 200 cycles of ck 3 load extended mode register load mode register 2 t mrd t mrd t rp t rfc t rfc 5 t is power-up: v dd and ck stable t = 200s high-z t ih dm dqs high-z a0?a9, a11, a12 ra a10 all banks ck ck# t ch t cl t ck v tt 1 v ref v dd v dd q command 6 lmr nop pre lmr ar ar act 5 t is t ih ba0 = h, ba1 = l t is t ih t is t ih ba0 = l, ba1 = l t is t ih ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) code code t is t ih code code 4 pre all banks t is t ih t0 t1 ta0 tb0 tc0 td0 te0 tf0 ( ) ( ) don?t care ba ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ra
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 85 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram timing diagrams figure 46: power-down mode notes: 1. once initialized, v ref must always be powered with in specified range. 2. if this command is a precharge (or if the devi ce is already in the idle state), then the power-down mode shown is precharge power-down. if this command is an active (or if at least one row is already active ), then the power-down mode shown is active power-down. 3. no column accesses are allowed to be in progress at the time power-down is entered. c k c k# c ommand valid 2 nop addr c ke dq dm dq s valid t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t i s enter 3 power-down mo d e exit power-down mo d e t ref c ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 ta0 ta1 ta2 t2 nop don ? t c are ( ) ( ) ( ) ( ) valid valid 1
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 86 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram timing diagrams figure 47: auto refresh mode notes: 1. pre = precharge, act = ac tive, ar = auto refresh, ra = row address, ba = bank address. 2. nop commands are shown for ease of illustra tion; other valid commands may be possible at these times. cke must be active during clock positive transitions. 3. nop or command inhibi t are the only commands allowed until after t rfc time, cke must be active during cl ock positive transitions. 4. ?don?t care? if a10 is high at this point; a10 must be high if more than one bank is active (i.e., must prec harge all active banks). 5. dm, dq, and dqs signals are all ?don ?t care?/high-z for operations shown. 6. the second auto refresh is not required and is only shown as an example of two back- to-back auto refresh commands. c k c k# c ommand 1 nop 2 valid valid nop 2 nop 2 pre c ke ra a0-a9, a11, a12 1 a10 1 ba0, ba1 1 bank(s) 4 ba ar nop 2, 3 ar 6 nop 2, 3 a c t nop 2 one bank all bank s c k t c h t c l t i s t i s t ih t ih t i s t ih ra dq 5 dm 5 dq s 5 t rf c 5 t rp t rf c t0 t1 t2 t3 t4 ta0 t b 0 ta1 t b 1t b 2 don ? t c are ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 87 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram timing diagrams figure 48: self refresh mode notes: 1. clock must be stable un til after the self refresh command has been registered. a change in clock frequency is allowed before ta0, provided it is within the specified t ck limits. regardless, the clock must be st able before exiting self refr esh mode. that is, the clock must be cycling wi thin specifications by ta0. 2. nops are interchangeable with desele ct commands, ar = auto refresh command. 3. auto refresh is not required at this point, but is hi ghly recommended. 4. device must be in the all banks idle sta te prior to entering self refresh mode. 5. t xsnr is required before any non-read command can be applied. that is only nop or deselect commands are allowed until tb1. 6. t xsrd (200 cycles of a valid clock with cke = high) is required before any read command can be applied. 7. as a general rule, any time self refresh mode is exited, the dram may not re-enter the self refresh mode until all rows have been re freshed via the auto refresh command at the distributed refresh rate, t refi, or faster. however, the foll owing exception is allowed. self refresh mode may be re-entered anytime after exiting, if the following conditions are all met: a. the dram had been in the self refresh mo de for a minimum of 200ms prior to exit- ing. b. t xsnr and t xsrd are not violated. c. at least two auto refresh commands are performed during each t refi interval while the dram remains out of self refresh mode. 8. if the clock frequency is changed during se lf refresh mode, a dll reset is required upon exit. 9. once the device is initialized, v ref must always be powered within specified range. c k 1 c k# c ommand 2 nop ar addr c ke dq dm dq s nop t rp 4 t c h t c l t c k t i s t i s t ih t i s t ih t i s enter s elf refre s h mo d e 7 exit s elf refre s h mo d e 7 t0 t1 1 ta1 don ? t c are ta0 1 t x s rd 6 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop valid 3 valid ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t x s nr 5 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ta2 t b 1t b 2t c 1 valid valid valid t i s t ih ( ) ( ) ( ) ( ) valid ( ) ( ) ( ) ( ) ( ) ( )
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 88 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram timing diagrams figure 49: bank read - without auto precharge notes: 1. do n = data-out from column n ; subsequent elements are provided in the programmed order. 2. bl = 4 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t5. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. the precharge command can only be applied at t5 if t ras minimum is met. 8. refer to figure 40 on page 79, figure 41 on page 80, and figure 42 on page 81 for detailed dqs and dq timing. ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras 7 t rc t rp cl = 2 dm t0 t1 t2 t3 t4 t5 t5n t6n t6 t7 t8 dq 1 dqs case 1: t ac ( min) and t dqsck ( min) case 2: t ac ( max) and t dqsck ( max) dq 1 dqs t rpre t rpre t rpst t rpst t dqsck ( min) t dqsck ( max) t lz ( min) t ac ( min) t lz ( min) do n t hz ( max) t ac ( max) do n nop 6 nop 6 command 5 3 act ra ra col n read 2 pre 7 bank x ra ra ra bank x bank x 4 act bank x nop 6 nop 6 nop 6 one bank all banks don?t care transitioning data x8: a12 x16: a11, a12 x4: a0?a9, a11, a12 x8: a0?a9, a11 x16: a0?a9
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 89 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram timing diagrams figure 50: bank read - with auto precharge notes: 1. do n = data-out from column n; subsequent elements are provided in the programmed order. 2. bl = 4 in the case shown. 3. enable auto precharge. 4. act = active, ra = row address, ba = bank address. 5. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 6. the read command can only be applied at t3 if t rap is satisfied at t3. 7. t rp starts only after t ras has been satisfied. 8. refer to figure 40 on page 79, figure 41 on page 80, and figure 42 on page 81 for detailed dqs and dq timing. ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih is ih ra t rc t rp 7 cl = 2 dm t0 t1 t2 t3 t4 t5 t5n t6n t6 t7 t8 dq 1 dqs case 1: t ac ( min) and t dqsck ( min) case 2: t ac ( max) and t dqsck ( max) dq 1 dqs t rpre t rpre t rpst t rpst t dqsck ( min) t dqsck ( max) t ac ( min) t lz ( min) do n t hz ( max) t ac ( max) do n nop 5 nop 5 command 4 3 act ra ra col n read 2,6 nop 5 bank x ra ra ra bank x act bank x nop 5 nop 5 nop 5 don?t care transitioning data t ras t lz ( min) t rcd, t rap 6 x8: a12 x16: a11, a12 x4: a0?a9, a11, a12 x8: a0?a9, a11 x16: a0?a9
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 90 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram timing diagrams figure 51: bank write - without auto precharge notes: 1. di n = data-in. from column n ; subsequent elements are provided in the programmed order. 2. bl = 4 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t8. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. see figure 43, ?data input timing? on page 81 for detailed dq timing. ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n nop 6 nop 6 command 5 3 act ra ra col n write 2 nop 6 one bank all banks bank x pre bank x nop 6 nop 6 nop 6 t dqsl t dqsh t wpst bank x 4 dq 1 dqs dm di b t ds t dh don?t care transitioning data t dqss (nom) t wpre t wpres x8: a12 x16: a11, a12 x4: a0?a9, a11, a12 x8: a0?a9, a11 x16: a0?a9
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 91 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram timing diagrams figure 52: bank write - with auto precharge notes: 1. di n = data-out from column n ; subsequent elements are pr ovided in the programmed order. 2. bl = 4 in the case shown. 3. enable auto precharge. 4. act = active, ra = row address, ba = bank address. 5. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 6. see figure 43 on page 81 for detailed dq timing. ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n nop 5 nop 5 command 4 3 act ra ra col n write 2 nop 5 bank x nop 5 bank x nop 5 nop 5 nop 5 t dqsl t dqsh t wpst dq 1 dqs dm di b t ds t dh t dqss (nom) don?t care transitioning data t wpres t wpre x8: a12 x16: a11, a12 x4: a0?a9, a11, a12 x8: a0?a9, a11 x16: a0?a9
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 92 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram timing diagrams figure 53: write - dm operation notes: 1. di n = data-in from column n ; subsequent elements are provided in the programmed order. 2. burst length = 4 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t8. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. see figure 43 on page 81 for detailed dq timing. ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t4n nop 6 nop 6 command 5 3 act ra ra col n write 2 nop 6 one bank all banks bank x pre bank x nop 6 nop 6 nop 6 t dqsl t dqsh t wpst bank x 4 dq 1 dqs dm di b t ds t dh don?t care transitioning data t dqss (nom) t wpres t wpre x8: a12 x16: a11, a12 x4: a0?a9, a11, a12 x8: a0?a9, a11 x16: a0?a9
09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 93 ?2000?2005 micron technology, inc. all rights reserved. 512mb: x4, x8, x16 ddr sdram package dimensions package dimensions figure 54: 66-pin plastic tsop (400 mil) notes: 1. all dimensions are in millimeters. 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. see detail a 0.10 0.65 typ 0.71 10.16 0.08 0.15 0.50 0.10 pin #1 id detail a 22.22 0.08 0.32 .075 typ +0.03 -0.02 +0.10 -0.05 1.20 max 0.10 0.25 11.76 0.10 0.80 typ 0.10 (2x) gage plane
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trad emarks of micron technology, inc. all other trademarks are the prope rty of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 512mb: x4, x8, x16 ddr sdram package dimensions 09005aef80a1d9e7 micron technology, inc., reserves the right to change products or specifications without notice. 512mbddrx4x8x16_2.fm - rev. j 1/06 en 94 ?2000?2005 micron technology, inc. all rights reserved. figure 55: 60-ball fbga (10 x 12.5mm) note: all dimensions are in millimeters. ball #1 id solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3% ag, 0.5% cu solder ball pad: ? .33 non solder mask defined mold compound: epoxy novolac substrate: plastic laminate 1.20 max 0.85 0.05 0.10 c c seating plane ball a1 id ball a1 c l c l .45 60x ? solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.40. ball a9 11.00 5.50 0.05 6.25 0.05 12.50 0.10 1.00 typ 6.40 1.80 ctr 0.80 (typ) 3.20 0.05 5.00 0.05 10.00 0.10

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